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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 顧孟愷(Mong-Kai Ku) | |
dc.contributor.author | Hsiu-Hung Lin | en |
dc.contributor.author | 林修鴻 | zh_TW |
dc.date.accessioned | 2021-06-08T05:02:11Z | - |
dc.date.copyright | 2010-08-31 | |
dc.date.issued | 2010 | |
dc.date.submitted | 2010-08-20 | |
dc.identifier.citation | [1] R.G. Gallager, “Low-Density Parity-Check Codes,” IEEE Transactions on Information Theory, vol. 8, pp. 21-28, Jan. 1962.
[2] R. Tanner, “A Recursive Approach to Low Complexity Codes”, IEEE Trans. Information Theory, pp. 533-547, Sep. 1981. [3] D. MacKay and R. Neal, “Good codes based on very sparse matrices,” in Cryptography and Coding, 5th IMA Conf., pp. 100-111, Springer, 1995. [4] D. MacKay and R. Neal, “Near Shannon Limit Performance of Low Density Parity Check Codes,' Electronics Letters, vol. 33, no. 6, pp. 457-458, 1997. [5] T. J. Richardson; A. Shokrollahi; R. Urbanke., “Design of capacity-approaching irregular low-density parity-check codes,” Information Theory, IEEE Transaction on, vol. 47, pp. 619-637, 2001. [6] T. J. Richardson; R. Urbanke., “The capacity of low-density-check codes under message-passing decoding,” Information Theory, IEEE Transaction on, vol. 47, pp. 599-618, 2001. [7] Sae-Young Chung; Forney, G.D., Jr.; T.J. Richardson; R. Urbanke, “On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit,” IEEE Communications Letters, Volume 5, Issue 2, pp. 58-60, Feb 2001. [8] Wang Lin; Xiao Juan; Guanrong Chen, “Density evolution method and threshold decision for irregular LDPC codes,” ICCCAS, pp. 25 – 28, June 2004. [9] Louay Bazzi; T. J. Richardson; R. Urbanke., “Exact Thresholds and Optimal Codes for the Binary-Symmetric Channel and Gallager’s Decoding Algorithm A,” Information Theory, IEEE Transaction on, vol. 50, 2004. [10] Hu. X. Y.; Eleftheriou, E.; D. Mackey, “Regular and irregular progressive edge-growth tanner graphs,” Information Theory, IEEE Transcations on, Vol. 51, pp. 386-398, 2005. [11] http://www.inference.phy.cam.ac.uk/mackey/PEG_ECC.html [12] Him Chen; Zhigang Cao, “A Modified PEG Algorithm for Construction of LDPC Codes with Strictly Concentrated Check-Node Degree Distributions,” Wireless Communications and Networking Conference, pp. 564-568, 2007. [13] Zhiyoung Fan; Weibo Zhang; Xing Liu; Haohui Cherg, “An improved algorithm for constructing QC-LDPC codes based on the PEG algorithm,” Communcations and Networking in China, pp. 1-4, 2009. [14] Shebl. S.; EL-Fishawy. N.; Elazm. A.A.; El-Samie. F.A., “A Random Construction of LDPC Codes Using a Sub-Optimal Search Algorithm,” Radio Science Conference, pp. 1-10, 2009. [15] Ratnayake, R. N. S.; Haratsch, E. F.; Gu-Yeou Wei, “Serial Sun-Product Architecture for Low-Density Parity-Check Codes,” Computer Communications and Networks, pp. 154-158, 2007. [16] Xiao-Yu Hu; Eleftheriou, E.; Arnold, D. M.; Dholakia, A, “Efficient implementations of the sum-product algorithm for decoding LDPC codes,” Global Telecommunications Conference, Vol. 2, pp. 1036-1036E, 2001. [17] S. Papaharalabos; P. Sweeney; B.G. Evans; P.T. Mathiopoulos; G. Albertazzi, A. Vanelli-Coralli, “Modified sum-product algorithms for decoding low-density parity-check codes,” IET Commun., pp. 294-300, 2007. [18] Zhang, T.; Wang, Z.; Parhi,K.K., “On finite precision implementation of low densidity parity check codes decoder,” ISCAS., Vol. 4, pp. 202-205, 2001. [19] Po-Hui Yang; Jung-Chieh Chen; Ya-Ting Chan; Ming-Yu Lin, “A simplified addition operation log-SPA LDPC decoder,” IEICE., 2008. [20] Myung Hun Lee; Jae Hee Han; Myung Hoon Sunwoo, ”New simplified sum-product algorithm for low complexity LDPC decoding,” SiPS, pp. 61-66, 2008. [21] Zarubica, R.; Hinton, R.; Wilson, S. G.; Hall, E. K., “Efficient quzntization schemes for LDPC decoders,” Militray Communications Conference, pp. 1-5, 2008. [22] http://www.xilinx.com/univ/xupv5-lx110t.htm [23] http://www.xilinx.com/support/documentation/ip_documentation/ug086.pdf | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23476 | - |
dc.description.abstract | 在LDPC編碼中,編碼的最小距離與編碼長度成正比。理論上,使用一個長編碼長度的LDPC編碼是我們所追求的。然而,卻有一些阻礙在長編碼長度的硬體設計。因此,在我的設計中,使用density evolution的方法在一個適合的編碼長度上來決定奇偶檢驗矩陣(parity check matrix)的節點級數分佈(node degree distribution pair),並在產生矩陣的過程中使其內含的cycle有著儘可能長的周長(girth)。而後,我們設計一個硬體的解碼器,此解碼器使用外部的DDR2 SDRAM記憶體使其可以存放大量的資料,包括奇偶檢驗矩陣、從通道中接收到的編碼以及解碼過程中所產生的大量資料。並且透過奇偶檢驗矩陣在記憶體中的置換,這個解碼器可以對不同的編碼進行解碼。最後,為了使每一種編碼都可以得到良好的編碼效益(coding gain),我們使用了sum-product algorithm。並且在硬體設計中選擇最小編碼效益損失的方式實作。 | zh_TW |
dc.description.abstract | It is well known the minimal LDPC code distance is increases by the code-length. Generally speaking, it is good to use a long code length but there are problems in long code-length hardware design. In my design, I use the density evolution to decide the suitable node degree distribution pair in several code-lengths and make the parity check matrix with as long as possible girth when I generated it. Then, I designed a decoder with an external DDR2 SDRAM. It provides the ability to storage the big matrix and the large number of variable information received in channel. Throwing the re-write external memory, it provides the ability to configure and can decode various LDPC codes. At least, in order to have as less as possible coding gain loss, I use the sum-product to be the decoding algorithm and do smallest coding gain lose in hardware design. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T05:02:11Z (GMT). No. of bitstreams: 1 ntu-99-R95922160-1.pdf: 962520 bytes, checksum: f3fea846aef4b665daa3b14e08a5b2b6 (MD5) Previous issue date: 2010 | en |
dc.description.tableofcontents | 中文摘要 i
ABSTRACT ii CONTENTS iii LIST OF FIGURES v LIST OF TABLES vi Chapter 1 Introduction 1 1.1 Low-Density Parity-Check Code Overview 1 1.2 Relative works 1 1.3 Thesis Organization 2 Chapter 2 Backgrounds 3 2.1 LDPC Codes 3 2.2 LDPC Decoding Algorithms 5 2.2.1 Sum-Product Algorithm 6 2.2.2 Horizontal Layered Scheduling Scheme 10 2.3 Density Evolution 13 Chapter 3 The Proposed Hardware Architecture 16 3.1 Architecture Overview 16 3.2 Xilinx Memory Interface Generator 17 3.3 Control Unit 19 3.3.1 Initialize Control Unit 19 3.3.2 Decoding Control Unit 20 3.4 Node-processor 20 3.4.1 Node-processor Architecture 20 3.4.2 Fix-point simulation 21 3.4.3 Phi( ) and Phi Inverse( ) Function Implementation 25 3.5 External Memory Architecture 26 Chapter 4 Simulation and Implementation Results 28 4.1 The Hardware Design Flow 29 4.2 The System Level Design 29 4.3 The RTL Level Design 30 4.4 The FPGA Level Design 30 Chapter 5 Conclusion 33 5.1 Conclusion 33 REFERENCE 34 | |
dc.language.iso | en | |
dc.title | 可重載的超長低密度奇偶校正碼解碼器 | zh_TW |
dc.title | A configurable very long codeword length LDPC decoder | en |
dc.type | Thesis | |
dc.date.schoolyear | 98-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 賴飛羆(Fei-pei Lai),廖俊睿(Jan-Ray Liao) | |
dc.subject.keyword | 低密度奇偶校驗碼,解碼器,sum-product,density evolution, | zh_TW |
dc.subject.keyword | Low-density parity-check (LDPC) code,sum-product,density evolution,decoder, | en |
dc.relation.page | 36 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2010-08-20 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
顯示於系所單位: | 資訊工程學系 |
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