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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 曹恆偉 | |
| dc.contributor.author | Bo-Cheng Guo | en |
| dc.contributor.author | 郭博誠 | zh_TW |
| dc.date.accessioned | 2021-06-08T05:01:24Z | - |
| dc.date.copyright | 2010-12-17 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-12-09 | |
| dc.identifier.citation | [1] 劉深淵, 楊清淵, 鎖相迴路, 滄海書局, 2006.
[2] Behazad Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill International Edition, 2001. [3] Behazad Razavi, “Design of Integrated Circuits for Optical Communications,” McGraw-Hill International Edition, 2003. [4] Nicola Da Dalt, Edwin Thaller, Peter Gregorius and Lajos Gazsi, “A Compact Triple-Band Low-Jitter Digital LC PLL With Programmable Coil in 130-nm CMOS,” IEEE J. Solid-State Circuits, , vol. 40, no. 7, pp. 1482-1490, July 2005. [5] Nicola Da Dalt, “A Design-Oriented Study of the Nonlinear Dynamics of Digital Bang-Bang PLLs,” IEEE Transactions on circuit and systems part-I: Regular Papers , vol. 52, no. 1, pp. 21-31, Jan. 2005. [6] Jeff L. Sonntag and John Stonick., “A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links,” IEEE J. Solid-State Circuits, vol. 8, no. 41, pp. 1867-1875, Aug. 2006. [7] J. Lee, K. S. Kundert, and B. Razavi., “Analysis and modeling of bang-bang clock and data recovery circuits,” IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1571-1580, Sep. 2004. [8] Robert Bogdan Staszewski and Poras T. Balsara, “All-Digital Frequency Synthesizer in Deep-Submicron CMOS,”Wiley-Interscience, 2003. [9] Volodymyr Kratyuk, Pavan Kumar Hanumolu, Kerem Ok,Un-Ku Moon, and Kartikeya Mayaram,“A Digital PLL With a Stochastic Time-to-Digital Converter,” IEEE Transactions on circuit and systems part-I: Regular Papers , vol. 56, no. 8, pp. 1612-1621, Aug. 2005. [10] Jawaharlal Tangudu, Sarma Gunturi, Saket Jalan, Jayawardan Janardhanan, Raghu Ganesan,Debapriya Sahu, Khurram Waheed, John Wallberg, Robert Bogdan Staszewski, “Quantization Noise Improvement of Time to Digital Converter (TDC) for ADPLL,” Proceedings of the IEEE Symposium on Circuits and Systems, pp. 1020-1023, May. 2009 [11] Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu and Hong-Yi Huang, “A Time-to-Digital Converter Using Multi-Phase-Sampling and Time Amplifier for All Digital Phase-Locked Loop,” Design and Diagnostics of Electronic Circuits and Systems, pp. 285-288, April 2010. [12] Chun-Ming Hsu, Matthew Z. Straayer and Michael H. Perrott, “A Low-Noise Wide-BW 3.6-GHz Digital Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation, ” IEEE Journal of Solid-State Circuits, vol. 43, no. 12, pp. 2776-2786, Dec. 2008. [13] Jim Dunning, Gerald Garcia, Jim Lundberg, and Ed Nuckolls, “An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors,” IEEE Journal of Solid-State Circuits, vol. 30, no. 4, pp. 412-422, Apr. 1995. [14] Ching-Che Chung and Chen-Yi Lee, “An All-Digital Phase-Locked Loop for High-Speed Clock Generation,” IEEE Journal of Solid-State Circuits, vol. 38, no. 2, pp. 347-351, Feb. 2003. [15] Thomas Olsson, and Peter Nilsson, “A Digitally Controlled PLL for SoC Applications,” IEEE Journal of Solid-State Circuits, vol. 30, no. 5, pp. 751-760, May. 2004. [16] Pao-Lung Chen, Ching-Che Chung, and Chen-Yi Lee, “A Portable Digitally Controlled Oscillator Using Novel Varactors,” IEEE Transactions on circuit and systems part- II: Express Briefs, vol. 52, no. 5, pp. 233-237, May 2005. [17] Konstantin A. Kouznetsov and Robert G. Meyer,“Phase Noise in LC Oscillators,” IEEE Journal of Solid-State Circuits, vol. 35, no. 8, pp. 1244-1248, Aug. 2000. [18] A. Hajimiri and T. H. Lee,“Design issues in CMOS differential LC oscillators,” IEEE Journal of Solid-State Circuits, vol. 34, no. 8, pp. 717-724, Aug. 1999. [19] Robert Bogdan Staszewski, Chih-Ming Hung, Dirk Leipold and Poras T. Balsara, “A First Multigigahertz Digitally Controlled Oscillator for Wireless Applications,” IEEE Transaction on Microwave Theory and Techniques, vol.51, no. 11, pp.2154-2164, Nov. 2003. [20] Robert Bogdan Staszewski, Dirk Leipold, Khurram Muhammad, and Poras T. Balsara, “Digitally Controlled Oscillator (DCO)-Based Architecture for RF Frequency Synthesis in a Deep-Submicrometer CMOS Process,” IEEE Transactions on circuit and systems part-II: Analog and digital signal Processing, vol.50, no. 11, pp.815-823, Nov. 2003. [21] T. Pittorino, Y. Chen, V. Neubauer, T. Mayer and L. Maurer, “A UMTS-compliant Fully Digitally Controlled Oscillator with 100Mhz Fine-Tuning Range in 0.13um CMOS,” International Solid-State Circuits Conference Digest of Technical Papers, pp. 770-779, Feb. 2006. [22] Terrence P. Kenny, Thomas A. D. Riley, Norman M. Filiol, and Miles A. Copeland, “Design and Realization of a Digital ΔΣ Modulator for Fractional-n Frequency Synthesis ,” IEEE Transactions on Vehicular Technology , vol. 48, no. 2, pp. 510-521, March 1999. [23] Mucahit Kozak and Izzet Kale, “A Pipelined Noise Shaping Coder for Fractional-N Frequency Synthesis ,” IEEE Transactions on Instrumentation and Measurement, vol. 50, no. 5 , pp. 1154-1161, Oct. 2001. [24] Yuan J., Svensson C., “High-speed CMOS circuit technique,” IEEE Journal of Solid-State Circuits , vol.24, no.1, pp.62-70, Feb. 1989. [25] Young I.A, Greason, J.K Smith, J.E, Wong, K.L, “A PLL clock generator with 5 to 110 MHz lock range for microprocessors,” Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International , pp.50-51, Feb. 1992 [26] Hooman Darabi, Shahla Khorram, Hung-Ming (Ed) Chien, Meng-An Pan, Stephen Wu, Shervin Moloudi, John C. Leete, Jacob J. Rael, Student Member, IEEE, Masood Syed, Robert Lee, Brima Ibrahim, Maryam Rofougaran, and Ahmadreza Rofougaran, “A 2.4-GHz CMOS Transceiver for Bluetooth,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 2016-2024, Dec. 2001. [27] Jingcheng Zhuang, Qingjin Du and Tad Kwasniewski, “A 3.3 GHz LC-Based Digitally Controlled Oscillator with 5kHz Frequency Resolution,” Asian Solid-State Circuits Conference , pp. 42-43, Nov. 2007. [28] W. J. Dally and J. Poulton, Digital System Engineering. Cambridge, U.K., Cambridge Univ. Press, 1998 [29] J. Lee, K. S. Kundert, and B. Razavi., “High-Speed Current-Mode Logic Amplifier Using Positive Feedback and Feed-Forward Source-Follower Techniques for High-Speed CMOS I/O Buffer,” IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 796-801, March 2005. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23421 | - |
| dc.description.abstract | 隨著CMOS製程科技的進步，鎖定相位迴路(Phase-locked Loop)已被廣泛應用於各種類型的系統，例如微處理器系統、記憶體積體電路、有線與無線網路信號傳輸…等等，都需要產生其規格所需的時脈頻率和相位，並以此時脈信號作為整體電路系統的動作時序基準。
一般常見的鎖定相位迴路分為類比鎖相迴路(Analog Phase-Locked Loop)與數位鎖相迴路(Digital Phase-locked Loop)。雖然傳統設計多採用前者，但數位鎖相迴路因具有抗製程變異性高和容易隨著製程轉移的優點，所以近年來電路發展的潮流也是盡量朝著全數位化前進。 本論文所設計為為基於二位元相位偵測器之數位鎖相迴路，核心的電路是使用互補式金氧半電晶體 0.18 μm的製程來實做晶片，而其餘數位演算法的電路則以Altera DE2-70的FPGA電路板來一起驗證。在輸入參考頻率為18.75MHz下，輸出頻率為2.4GHz時，時脈峰對峰抖動和方均根抖動分別為37ps和7ps，下線的晶片面積為1000 μm x 750 μm(包含Pad)，功率消耗為55mW(含buffer)。 | zh_TW |
| dc.description.abstract | As the progress of CMOS technology, phase-locked loop has been widely implemented in many applications, such as mems, memory integrated chip and communication systems. It is used to generate the clock frequency and phase in a system. The traditional structure of a phase-locked loop could be classified into two kinds. One is analog phase-locked loop (APLL), the other is all-digital phase-locked loop (ADPLL). Although the former is usually adopted by conventional ic designer, ADPLL is more suggested in recently years because of its good tolerance to PVT variations and less sensitive to supply noise. Furthermore, ADPLL can be portable to new technology. It can reduce the development time for system-on-chip applications.
This thesis proposed an ADPLL based on bang-bang phase detector with a frequency detector. The chip is fabricated in TSMC 0.18μm CMOS technology with an area of 1000 μm x 750 μm. Under 1.8V supply, the power dissipation is 43mW with output buffer. The measured output clock’s rms and peak-to-peak jitter are 7ps and 37ps at 2.4GHz. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T05:01:24Z (GMT). No. of bitstreams: 1 ntu-99-R96943156-1.pdf: 2778000 bytes, checksum: 344b79bfed588d83fe0a26f7c6709469 (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | 中文摘要 ------------------------------------- I
Abstract -------------------------------------II Contents-------------------------------------III List of Figures -------------------------------V List of Tables ------------------------------ IX Chapter 1 緒論---------------------------------1 1.1 動機 --------------------------------------1 1.2 論文架構 ----------------------------------5 Chapter 2 全數位鎖相迴路之介紹與分析-----------6 2.1 數位鎖相迴路介紹 --------------------------6 2.2數位鎖相迴路的特性分析 ---------------------7 2.3數位控制振盪器的介紹 ----------------------11 Chapter 3 全數位鎖相迴路之設計 ---------------20 3.1 改進後的數位鎖相迴路架構------------------21 3.1.1頻率追蹤模式---------------------------- 22 3.1.2相位鎖定模式-----------------------------25 3.2 模擬結果----------------------------------27 Chapter 4 量測環境與量測結果------------------46 4.1 設計流程----------------------------------46 4.2 量測環境考量----------------------------- 48 4.2.1 下線晶片佈局圖--------------------------48 4.2.2下線晶片模擬環境-------------------------50 4.2.3 印刷電路板製作--------------------------51 4.3 下線電路量測結果--------------------------52 4.4數位電路設計流程---------------------------56 4.5 硬體驗證環境和實驗結果------------------- 57 4.6 總結--------------------------------------63 Chapter 5 總結與展望--------------------------64 5.1總結---------------------------------------64 5.2 展望------------------------------------- 64 Bibliography--------------------------------- 68 | |
| dc.language.iso | zh-TW | |
| dc.subject | FPGA電路板 | zh_TW |
| dc.subject | 數位鎖定相位迴路 | zh_TW |
| dc.subject | 二位元相位偵測器 | zh_TW |
| dc.subject | bang-bang Phase Detector | en |
| dc.subject | FPGA board | en |
| dc.subject | Digital Phase-locked Loop | en |
| dc.title | 基於二位元相位偵測器之全數位鎖相迴路 | zh_TW |
| dc.title | An All-Digital Phase-locked Loop Based on Bang-bang Phase Detector | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 99-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李揚漢,陳建中,黃崇禧 | |
| dc.subject.keyword | 數位鎖定相位迴路,二位元相位偵測器,FPGA電路板, | zh_TW |
| dc.subject.keyword | Digital Phase-locked Loop,bang-bang Phase Detector,FPGA board, | en |
| dc.relation.page | 71 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2010-12-09 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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