在固態硬碟上以需求分頁為基礎的快閃記憶體轉換層設計之設計空間探索

Abstract

隨著快閃記憶體在容量和可靠性上的不斷進步以及相較於傳統硬碟更高的效能和耗電量，快閃記憶體在許多裝置上的應用越來越受歡迎。但是快閃記憶體有許多與傳統硬碟不同的特性使得我們必須開發一個低成本的快閃記憶體轉換層以把邏輯位置轉換為實體位置。 為了能夠降低快閃記憶體(flash)轉換層使用靜態記憶體(SRAM)的量，在此論文上我們提出了考慮空間侷限性的快閃記憶體轉換層(Spatial-locality Aware FTL, SAFTL)。考慮空間侷限性的快閃記憶體轉換層將邏輯位置對應到實體位置的對應表(mapping table)放在快閃記憶體中而不是放在靜態記憶體。僅使用不同的快取列(cache line)大小的快取把未來會使用到的對應(mapping entry)快取到靜態記憶體中，並且調整快取列大小使得未來會被用到的資料都能夠被快取到。我們分析了不同快取列大小對於快取命中率(hit rate)和效能的影響，發現了比較高的快取命中率不一定會帶來比較高的效能。實驗結果顯示出了考慮空間侷限性的快閃記憶體轉換層可以達到與前人提出的方法相同的效能卻只需要9.1% 的靜態記憶體大小。

Flash memory has become a popular storage alternative for many devices with the continuing improvements on its capacity, reliability, higher performance, and much lower power consumption than mechanical hard drives. But special characters of flash memory lead the need to design a low cost Flash Translation Layer(FTL) to translate logical address to physical address. In this paper, we proposed a novel FTL scheme named Spatial-locality Aware FTL(SAFTL), which can exploit spatial locality for FTL to save SRAM size. Instead of putting whole mapping table in SRAM, SAFTL stores mapping table in flash and uses a cache with multiple cache line sizes to cache mapping entries which may be used in the future. SAFTL adjusts the cache line size to make sure all data which will be used in the near future will be cached. We analyzed the impact of cache line size to hit rate and performance. An interesting finding is high hit rate doesn’t lead to high performance. Our evaluation results show that SAFTL can achieve same performance as previous works with only 9.1% SRAM size.