45奈米以下之元件其應力與應變的模擬與分析

Abstract

利用電晶體的微縮來改善互補式金屬氧化層半導體場效電晶體的性能已經至少三十年了，由於元件的微縮已經幾乎達到了物理的極限，工業界與研究團體開始積極的找尋一些非傳統的解決方法。 其中藉由改變矽通道內的應變與應力來達到元件性能的改善，是一個已經廣泛被運用在現行製程技術中的解決方法。 接觸蝕刻停止層是其中一種應變與應力工程，自九十奈米的技術開始，接觸蝕刻停止層就開始被用來改善互補式金屬氧化層半導體場效電晶體的性能，而這個接觸蝕刻停止層是由氮化物所組成，原本是用於金屬接觸的蝕刻停止。 另一種應變與應力工程是應力記憶技術，這是少數對Ｎ型場效電晶體的性能可以改善的技術之一，而這項技術也是現今製程中不可或缺的技術之一，它不只用在傳統的多晶矽閘極，也用在金屬嵌入多晶矽閘極還有金屬閘極的技術中。有兩個主要的理論支持著應力記憶技術，一個是朔性變形模型，另一個是多晶矽閘極的體積膨脹。 最後，我們討論一些其他能改善元件性能的應力與應變的模擬，如接觸蝕刻停止層厚度對元件的影響，多晶矽閘極之間的距離對元件的影響，對本質應力成份的分解，參雜物限制層技術，多重的應力記憶技術，源極與汲極中的應力記億技術，絕緣暈用於防止淺溝渠隔離層的效應。

Transistor scaling down has been the principal factor in driving CMOSFET performance improvement for more than thirty years. Approaching the fundamental limits of transistor scaling leads the industry and the research community to actively search for alternative solutions. The use of strained Si obtained by stress engineering seems to be one solution to achieve transistor performance improvements. One of stress engineering is contact etch stop layer (CESL), since the 90nm CMOS technology node, the CESL is used as a stress-engineering booster that enables transistor improvement, and the CESL consists in a nitride layer used to stop the etching of the metallic contact. The other one of stress engineering is stress memorization technique (SMT), the SMT is one of the few strain techniques for N-FET performance enhancement, and it has been a necessary technique in recent high-performance technology not only for conventional poly-gates, but also for MIPS (Metal Inserted Poly-silicon Stack) and metal gates. There are two major theory support SMT, one is plastic deformation model and the other one is poly-gate volume expansion. Finally, other simulations for strain enhancement techniques are discussed. Such as the influence of CESL thickness and poly spacing, decomposition of the intrinsic stress, the Dopant Confinement Layer (DCL) technique, Multi-SMT, SMT in source and drain, the insulating halo for shallow trench isolation (STI).