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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 劉致為(Chee Wee Liu) | |
dc.contributor.author | Yen-Ting Chen | en |
dc.contributor.author | 陳彥廷 | zh_TW |
dc.date.accessioned | 2021-06-08T04:41:26Z | - |
dc.date.copyright | 2009-08-19 | |
dc.date.issued | 2009 | |
dc.date.submitted | 2009-08-11 | |
dc.identifier.citation | Chapter 1
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Okhonin, M. Nagoga, E. Carman, R. Beffa, and E. Faraoni, “New Generation of Z-RAM,” IEEE International Electronic Device Meeting, pp. 925-928, 2007. [3.4] K.-W. Song, H. Jeong, J.-W. Lee, S.-I. Hong, N.-K. Tak, Y.-T. Kim, Y.-L. Choi, H.-S. Joo, S.-H. Kim, H.-J. Song, Y.-C. Oh, W.-S. Kim, Y.-T. Lee, K. Oh, and C. Kim, “55 nm Capacitor-less 1T DRAM Cell Transistor with Non-Overlap Structure,” IEEE International Electronic Device Meeting, pp. 797-800, 2008. [3.5] H.-J. Bae, H.- J. Song, Y.-L. Choi, S.-H. Kim, S.-I. Hong, C.-W. Oh, D.-W. Kim, G. Jin, K.-S. Oh, and W.-S. Lee, “Evaluation of 1T RAM using Various Operation Methods with SOONO (Silicon-On-ONO) device,” IEEE International Electronic Device Meeting, pp. 805-808, 2008. [3.6] J.-W. Han, S.-W. Ryu, S. Kim, C.-J. Kim, J.-H. Ahn, S.-J. Choi J.-S. Kim, K.-H. Kim, G.-S. Lee, J.-S. Oh, M.-H. Song, Y.-C. Park, J.-W. Kim and Y.-K. Choi “A Bulk FinFET Unified-RAM (URAM) Cell for Multifunctioning NVM and Capacitorless 1T-DRAM,” IEEE Electron Device Lett., vol. 29, no. 6, pp. 632-634, June. 2008. [3.7] Eiji Yoshida and Tetsu Tanaka, “A Sesign of a capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory,” IEEE International Electronic Device Meeting, pp. 913-916, 2003. [3.8] M. Valdinoci, L. Colalongo, G. Baccarani, G. Fortunato, A. Pecora and I. Policicchio “Floating Body Effects in Polysilicon Thin-Film Transistors,” IEEE Electron Device Lett., vol. 44, no. 12, pp. 2234-2241, Dec. 1997. [3.9] M. Bawedin, S. Cristoloveanu and D. Flandre “Innovating SOI memory devices based on flodying-body effects,” Solid-State Electronics, pp. 1252-1262, Sept. 27 2007. [3.10] M. R. Tack, M. Gao, C. L. Claeys and G. J. Declerck “The Multistable Charge-Controlled Memory Effect in SOI MOS Transistors at Low Temperatures,” IEEE Trans. Electron Devices, vol. 37, no. 5, pp. 1373-1382, May 1990. [3.11] M. Nagoga, S. Okhonin, C. Bassin, P. Fazan, W. Xiong, C. R. Cleavelin, T. Schulz, K. Schruefer, M. Gostkowski, P. Patruno and C. Maleville “Retention Characteristics of Zero-capacitor RAM (Z-RAM) cell based on FInFET and Tri-Gate devices,” IEEE International SOI Conference, pp. 203-204, 2005. [3.12] A. Nayfeh, V. Koldyaev, P. Beaud, M. Nagoga and S. Okhonin “A Leakage Current Model for SOI based Floating Body Memory that Includes the Poole-Frenkel Effect,” IEEE International SOI Conference, pp. 75-76, 2008. Chapter 4 [4.1] T.-Y. Huang, A. G. Lewis, I.-W. Wu, A. Chiang and R. H. Bruce, “A New Stack Capacitor for Polysilicon Active Matrix Arrays,” IEEE International Electronic Device Meeting, pp. 357-360, 1989. [4.2] Z. Meng, M. Wang, H. S. Kwok, and M. Wong, “Re-Crystallized Metal-Induced Laterally Crystallized Polycrystalline Silicon for System-on-Panel Applications,” SID Symposium Digest, vol. 31, pp. 531-534, 2000. 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Sun, P.-S. Kuo, Y.-T. Chen, C. W. Liu, Y.-J. Hsu, and J.-S. Chen, “Dynamic Bias Temperature Instability of p-channel Polycrystalline Silicon Thin-film Transistors,” 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA2009), Suzhou, China, July 6-10, 2009. [4.12] Y. Toyota, T. Shiba and M. Ohkura, “Effects of the Timing of AC Stress on Device Degradation Produced by Trap States in Low-Temperature Polycrystalline-Silicon TFTs,” IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1766-1771, Aug. 2005. [4.13] K.-M. Chang, Y.-H. Chung and G.-M. Lin, “Hot Carrier Induced Degradation in the Low Temoerature Processed Polycrystalline Silicon Thin Film Transistors Using the Dynamic Stress,” J. Appl. Phys., vol. 41, no. 4A, pp. 1941-1946, 2002. [4.14] K.-C. Moon, J.-H. Lee and M.-K. Han, “The Study of Hot-Carrier Stress on Poly-Si TFT Employing C-V Measurement,” IEEE Trans. Electron Devices, vol. 52, no. 4, pp. 512-517, Apr. 2005. [4.15] F. V. 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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23090 | - |
dc.description.abstract | 近年來低溫多晶矽薄膜電晶體在平面顯示器驅動電路中廣為使用,利用準分子雷射結晶法可將成長於玻璃基板上的非晶矽重新結晶為多晶矽,藉以提高載子移動率,使達到先進顯示技術。首先所要研究為結晶過程中所產生的晶粒邊界對元件所造成的電性影響,我們將利用基本分析模型和電流傳導機制去解釋由閘極和汲極引發的能障降低效應所主導的次臨界特性以及在累積區中的漏電流機制。
現今無電容記憶體已經被廣泛使用在存取設備中,但由於資料儲存時間短,須不斷重複刷新資料,將會大幅增加能量損耗,為此我們發明了利用薄膜電晶體來進行非揮發記憶體的操作,其原理為調變晶粒邊界在累積區時的能障,來改變不同累積電流。此記憶體擁有非揮發與可重複操作特性以及不需額外製程將是設計實用化的一大助力。 最後,我們將對元件的穩定性及可靠度進行研究,並討論低溫多晶矽薄膜電晶體於施加汲極電壓應力下的所引起的雪崩效應。其劣化效應程度與偏壓大小、通道長度以及溫度有關。主要衰退原因為在靠近汲極之區域,因高電場引發之衝擊游離所產生之熱電子電洞對注入氧化層和主動層接面以及晶粒邊界中產生缺陷。 | zh_TW |
dc.description.abstract | In recent years, low temperature polycrystalline silicon thin film transistors (LTPS TFTs) have been widely used in flat panel display driving circuit. The a-Si film is recrystallized to the poly-Si film by excimer laser crystalline method and achieves the advanced display technology. First, we will discuss the basic model and current conduction mechanism of grain boundaries in the poly-Si film. Due to the influence of grain boundaries, the subthreshold characteristics are explained by the gate and drain induced barrier lowering. The leakage current is also investigated by trap generation and emission in the drain depletion region.
A novel capacitor-less random access memory has been developed in recent years and used in the storage devices. This memory exhibits data remanence, but is still volatile in the conventional sense that data is eventually lost when the memory is not powered. The nonvolatile memory is utilized extensively in the electronic systems because of its long retention time and low power consumption. Therefore, we constructed a new memory device which is compatible with TFT fabrication processes. The new operation mode is to realize the memory characteristics by operating the poly-Si TFTs in the accumulation region. The application of capacitorless non-volatile memory based on poly-Si TFTs shows more advantages, such as low operation current, long retention time, low power consumption, and excellent endurance characteristics. Finally, drain avalanche hot carrier stress of n-channel TFTs is investigated. This degradation depends with the drain stress voltage, channel length and stress temperature. The stress-induced degradation in the on-state current may be attributed to the hot carriers inject into the grain boundaries to create amount defect states. The threshold voltage shift can be explained that the hot carriers inject to the interface and create the negative interface states. The reliability issue must be taken into consideration for process and circuit design. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T04:41:26Z (GMT). No. of bitstreams: 1 ntu-98-R96943084-1.pdf: 1617949 bytes, checksum: 9518f4780be736c356ed04b67377f5b0 (MD5) Previous issue date: 2009 | en |
dc.description.tableofcontents | List of Figures VI
List of Tables XI Chapter 1 Introduction 1.1 Background and Motivation 1 1.2 Organization of thesis 2 Chapter 2 Grain boundaries in Poly-Si TFTs 2.1 Introduction 4 2.2 The Basic Model of Grain Boundaries 5 2.3 Carrier Transport Mechanism in Poly-Si Film 10 2.4 Subthreshold Characteristics of Thin Film Transistors 17 2.5 Leakage Current of Thin Film Transistors 23 2.6 Summary 28 Chapter 3 Basic Operation of Non-volatile Capacitorless Memory by Poly-Si TFTs 3.1 Introduction 29 3.2 Experimental Setup 31 3.3 Basic Program/Ease Mechanisms 38 3.4 Bias Optimization and Output Characteristics 40 3.5 Reliability of Non-volatile memory 47 3.6 Summary 52 Chapter 4 Drain Avalanche Hot Carrier Stress of Poly-Si TFTs 4.1 Introduction 53 4.2 Experimental Procedures 54 4.3 Results and Discussion 56 4.4 Summary 67 Chapter 5 Summary and Future Work 5.1 Summary 68 5.2 Future Work 69 References | |
dc.language.iso | en | |
dc.title | 利用低溫複晶矽薄膜電晶體之非揮發性無電容記憶體 | zh_TW |
dc.title | The Non-volatile Capacitorless Memory by Poly-Si Thin Film Transistors | en |
dc.type | Thesis | |
dc.date.schoolyear | 97-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 汪大暉(Ta-Hui Wang),蔡銘進(Ming-Jin Tsai),陳其賢(Chi-Shian Chen) | |
dc.subject.keyword | 薄膜電晶體,晶粒邊界,無電容記憶體,非揮發性記憶體,雪崩效應, | zh_TW |
dc.subject.keyword | thin film transistors,grain boundary,capacitorless memory,non-volatile memory,avalanche effect, | en |
dc.relation.page | 80 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2009-08-12 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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