請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23002完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | |
| dc.contributor.author | Chien-Chun Huang | en |
| dc.contributor.author | 黃健群 | zh_TW |
| dc.date.accessioned | 2021-06-08T04:37:16Z | - |
| dc.date.copyright | 2009-08-20 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-08-17 | |
| dc.identifier.citation | [1] Mikael. Gustavsson, J. Jacob Wikner and Nianxiong Nick Tan, CMOS Data converters for communications, Kluwer Academic Publishers, Boston, 2000.
[2] David A. Johns and Ken Martin, Analog Integrated Circuit Design, John Wiley and Sons Inc., 1997. [3] C. H. Lin and K. Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1948-1958, Dec. 1998. [4] M. J. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, no. 12, pp. 1433-1440, Oct. 1989. [5] J. Vandenbussche, G. Van der Plas, W. Daems, A. Van den Bosch, G. Gielen, M. Steyaert and W. Sansen, “An 80MHz 8-bit CMOS D/A converter,” IEEE Transactions on Circuits and System-II, vol. 48, no. 3, Mar. 2001. [6] C. Y. Huang, T. T. Hou and H. Y. Wang, “A 12-bit 250MHz current-steering DAC,” ASIC, 2005, ASICON 2005, 6th International Conference, vol. 1, pp. 411-414, Oct. 2005. [7] J. Yuan and C. Svensson, “New single-clock CMOS latches and flipflop with improved speed and power savings,” IEEE J. Solid-State Circuits, vol. 32, pp. 62-69, Dec. 1997. [8] J. Deveugele and M. Steyaert, “A 10-bit 250-MS/s binary-weighted current-steering DAC,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 320-329, Feb. 2006. [9] J. Bastos, A. M. Marques, M. S. J. Steyaert and W. Sansen, “A 12-bit intrinsic accuracy high speed CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1959-1969, Dec. 1998. [10] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001. [11] M. J. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1440, Oct. 1989. [12] B. Razavi, Principles of Data Conversion System Design, New York: IEEE Press, 1995. [13] A. Van den Bosch, M. S. J. Steyaert and W. Sansen, “SFDR-bandwidth limitions for high-speed high resolution current-steering CMOS D/A converters,” in Proc. IEEE 2000 Int. Symp. Circuit and Systems (ISCAS), vol. 4, pp. 105-108, 2000. [14] P. R. Gray, Analysis and Design of Analog Integrated Circuits, John Wily and Sons Inc., 2009. [15] J. Bastos, M. Steyaert, A. Pergoot and W. Sansen, “Influence of die attachment on MOS transistor matching,” IEEE Tran. Semiconduct. Manufac., pp. 209-217, May. 1997. [16] G. Van Der Plas, J. Vandenbussche, W. Sansen, M. Steyaert and G. Gielen, “A 14-bit intrinsic accuracy Q2 random walk CMOS DAC,” IEEE J. Solid-State Circuits, vol. 34, pp. 1708-1717, Dec. 1999. [17] Y. Cong and R. L. Geiger, “Switching Sequence Optimization for Gradient Error Compensation in Thermometer-Decoded DAC Array,” IEEE Tran. Circuit System II, vol. 47, pp. 585-595, Jul. 2000. [18] Mark I. Montrose, EMC and the Printed Circuit Board Design, Theory, and Layout Made Simple, IEEE Press, 1999. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/23002 | - |
| dc.description.abstract | 這篇論文的提出了一個高速八位元電流引導式數位類比轉換器，使用區段化電流切換式架構，其中包含高五位元的溫度計碼及低三位元的二進制碼，這樣的設計不僅可以保持原本電流切換式架構的優點，更可以達到降低消耗功率的好處。這次設計的數位類比轉換器其架構是使用所提出的新的開關切換順序方式來實現。這個新的開關切換方式是將高位元的電流源分成八個部份來補償二次誤差並且使用整體非線性失真邊界演算法來達到最佳化的目的。
這個數位類比轉換器採用UMC 90nm 1P9M mixed-signal CMOS製程來實現，整體晶片核心面積為0.013mm2，加入PADs之後0.415mm2。整體非線性失真及差動非線性失真分別為0.19LSB和0.26LSB。當操作在10億赫茲及輸入頻率為9.25百萬億赫茲時，其無雜散動態範圍達到49.2dB。功率消耗在1伏操作下為8.2毫瓦。 | zh_TW |
| dc.description.abstract | This thesis proposes an 8-bit 1GHz digital-to-analog converter with a segmented current steering architecture that consists of two parts, the upper 5-bit thermometer code and the lower 3-bit binary-weighted code. The design not only keeps the advantages of current steering architecture, but also consumes lower power. The DAC architecture is implemented by the proposed switching sequence. The new switching sequence divides the upper 5-bit current source into eight unary current source to compensate quadratic error and also uses integral non-linear (INL) bounded algorithm to optimize the INL characteristic.
This DAC has been implemented in a 90nm 1P9M mixed-signal CMOS process provided by UMC, with active area of 0.013mm2 and total area including PADs is 0.415mm2.The INL and differential non-linear (DNL) are 0.19 and 0.26 LSB, respectively. The spurious-free dynamic range (SFDR) is 49.2dB when the update rate is 1GHz and the input frequency is 9.25MHz. The power consumption is 8.2mW with a supply voltage of 1V. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T04:37:16Z (GMT). No. of bitstreams: 1 ntu-98-J95921038-1.pdf: 3883479 bytes, checksum: 22470279ec048cabe153df004e7bf1eb (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | 中文摘要...................................................I
Abstract.................................................III Contents...................................................V List of Figures...........................................IX List of Tables..........................................XIII Chapter 1 Introduction....................................1 1.1 Motivation.............................................1 1.2 Thesis Organization....................................2 Chapter 2 Fundamental Concepts and Architectures of DAC...3 2.1 Introduction...........................................3 2.2 Ideal DAC..............................................4 2.3 Static Performance.....................................5 2.4 Dynamic Performance....................................8 2.5 Frequency Domain Performance..........................11 2.6 Digital-to-Analog Converter Architecture..............13 2.6.1 Resistor-String DAC.................................14 2.6.2 R-2R Ladder DAC.....................................15 2.6.3 Charge Redistribution DAC...........................16 2.6.4 Current-Steering DAC................................17 2.6.5 Segmented architecture DAC..........................19 Chapter 3 Circuit Design Techniques of Current-Steering DAC.......................................................21 3.1 Digital Circuit Design................................21 3.1.1 Segmentation of Current-Steering DAC................22 3.1.2 The Proposed DAC Architecture.......................27 3.1.3 TSPC DFF............................................29 3.1.4 Binary-Thermometer Decoder..........................30 3.1.5 Deglitch Latch......................................31 3.1.6 Clock Tree..........................................33 3.2 Analog Circuit Design.................................34 3.2.1 Design flow of Unit Current Source..................34 3.2.1.1 INL Yield.........................................35 3.2.1.2 Random Error......................................38 3.2.1.3 Finite Output Impedance of Current Source.........40 3.2.2 Bias Circuit........................................43 3.3 The Proposed Switching Sequence of Current Source Array to Compensate Quadratic Error.............................45 3.3.1 Systematic Error....................................45 3.3.2 Quad Quadrant Switching Sequence....................47 3.3.3 The Proposed Switching Sequence.....................49 3.3.4 The Proposed Switching Sequence with INL Bounded Algorithm.................................................50 3.4 Layout Implementation.................................55 3.5 Simulation Results....................................58 Chapter 4 Chip Measurement Results.......................61 4.1 Evaluation Board Design...............................61 4.1.1 Grounding...........................................63 4.1.2 Bypassing and Decoupling............................64 4.1.3 Digital Input and Analog Output.....................65 4.2 Measurement Setup.....................................66 4.2.1 Static Measurement Setup............................66 4.2.2 Dynamic Measurement Setup...........................67 4.3 Measurement Results...................................68 4.3.1 Static Measurement Results..........................68 4.3.2 Dynamic Measurement Results.........................69 Chapter 5 Conclusion and Future Work.....................75 5.1 Conclusion............................................75 5.2 Futrue Work...........................................76 References................................................77 | |
| dc.language.iso | en | |
| dc.subject | 數位類比轉換 | zh_TW |
| dc.subject | 整體非線性失真 | zh_TW |
| dc.subject | 整體非線性邊界演算法 | zh_TW |
| dc.subject | 差動非線性失真 | zh_TW |
| dc.subject | 無雜散動態範圍 | zh_TW |
| dc.subject | differential non-linear | en |
| dc.subject | spurious-free dynamic range | en |
| dc.subject | digital-to-analog converter | en |
| dc.subject | integral non-linear | en |
| dc.subject | integral non-integral bounded algorithm | en |
| dc.title | 具補償二次誤差之高速八位元電流引導式數位類比轉換器 | zh_TW |
| dc.title | A Quadratic Error Compensation in High-Speed 8-bit Current-Steering Digital to Analog Converter | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 陳昭宏,陳怡然 | |
| dc.subject.keyword | 數位類比轉換,整體非線性失真,整體非線性邊界演算法,差動非線性失真,無雜散動態範圍, | zh_TW |
| dc.subject.keyword | digital-to-analog converter,integral non-linear,integral non-integral bounded algorithm,differential non-linear,spurious-free dynamic range, | en |
| dc.relation.page | 79 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2009-08-17 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-98-1.pdf 未授權公開取用 | 3.79 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。