900 MHz 帶通三角積分調變器使用數位輔助迴路濾波器

Abstract

本論文的第一部份，提出了一個新架構的四階的連續時間三角積分調變器，此調變器應用在RF端的高速類比數位轉換器，不經過降頻至基頻，直接在高頻載波上做數位化，而在此調變器的架構上使用數位輔助濾波器，將使回授數位類比轉換器(feedback DAC)從原本四個降至兩個，同時可只使用不歸零數位類比轉換器(NRZ- DAC)，減少時間抖動對系統效能的影響。此三角積分調變器使用台積電0.13微米互補式金氧半製程所實現，使用微米互補式金氧半製程可提供和後端數位電路整合至單一晶片的可能性。此高速類比數位轉換器使用3.6 GHz的取樣頻率和900 MHz的輸入信號，在200 kHz的頻寬下可以得到67 dB的訊號雜訊比和55 dB的動態範圍。在1.2 V的供應電壓下，此晶片需要消耗51 mW的功率。 本論文的第二部份，提出了一個新的數位補償濾波器來改善在連數時間三角積分器中的特有問題，延遲時間的影響，此補償技巧觀念來自在負回授系統中相位補償的概念，在數位端做一個補償濾波器，同時部分雜訊轉移函數(NTF)會被數位端負責，將使類比電路的漂移效應(RC variation)減低，並發現有降低數位類比轉換器(DAC)的回授數目的好處。在電路實現上，此數位補償濾波器可利用簡單的邏輯架構完成，又可產生使用數位類比轉換器時的隨機化，降低因數位類比轉換器的不對稱所產生的諧波(harmonic distortion)，目前系統模擬已證實此模型對延遲時間補償的有效性，和電路上實現對數位類比轉換器的隨機化的產生。

This thesis presents the design and circuit implementation of a fourth-order continuous-time bandpass delta-sigma ADC with only two non-return-to-zero (NRZ) feedback DACs and a digitally-aided loop filter, to replace the four original feedback paths. The goal of this work is to reduce the effect of clock jitter in RF delta-sigma ADC. This ADC applies for direct digitization of the RF signal at the 900-MHz center frequency by using the 3.6-GHz sampling frequency. A prototype modulator is fabricated in 0.13-um CMOS process. A CMOS implementation of the modulator provides the feasibility of integrating the following DSP blocks on the same chip. Measurement results of this ADC show the SNR of 67 dB in signal bandwidth of 200 kHz around 900-MHz frequency, while the whole ADC consumes 42.5 mA from 1.2-V supply voltage. A newly proposed prototype which can tolerate excess-loop delay to at most one period without any compensated path is described in the second part of this thesis. It is based on the idea that placing a zero to compensate the phase caused by loop delay in a negative feedback system. The realization of this zero is in digital domain, and part of the noise transfer function (NTF) in the analog domain is pushed to the digital domain to reduce the time-constant shifts in analog circuit. Moreover, the number of required DAC units is reduced, and the simple logic implementation of the compensation digital filter provides implicit DAC randomization. System simulation results display the effectiveness of the proposed model.