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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/22911完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳少傑(Sao-Jie Chen) | |
| dc.contributor.author | Yueh-Chi Lin | en |
| dc.contributor.author | 林玥其 | zh_TW |
| dc.date.accessioned | 2021-06-08T04:33:12Z | - |
| dc.date.copyright | 2009-08-20 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-08-20 | |
| dc.identifier.citation | [1] Ying-Cherng Lan, Shih-Hsin Lo, Yueh-Chi Lin, Yu-Hen Hu, and Sao-Jie Chen, “BiNoC: A Bidirectional NoC Architecture with Dynamic Self-Reconfigurable Channel,” Proc. of ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pp. 266-275, May 2009.
[2] Chen-Ling Chou and Radu Marculescu, “Contention-aware Application Mapping for Network-on-Chip Communication Architectures,” Proc. of IEEE International Conference on Computer Design (ICCD), pp. 164-169, Oct. 2008. [3] Tang Lei and Shashi Kumar, “A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture,” Proc. of Euromicro Conference on Digital System Design (DSD), pp. 180-187, Aug. 2003. [4] Jingcao Hu and Radu Marculescu, “Exploiting the Routing Flexibility for Energy/Performance-Aware Mapping of Regular NoC Architectures,” Proc. of Conference on Design, Automation & Test in Europe (DATE), pp. 688-693, Apr. 2003. [5] Jingcao Hu and Radu Marculescu, “Energy-Aware Mapping for Tile-based NoC Architectures Under Performance Constraints,” Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), pp.233-239, Jan. 2003. [6] Cesar Marcon, Marcio Kreutz, Altamiro Susin, and Ney Calazans, “Models for Embedded Application Mapping onto NoCs,” Proc. of IEEE International Workshop on Rapid System Prototyping (RSP), pp. 17-23, Jun. 2005. [7] Cesar Marcon, Ney Calazans, Fernando Moraes, Altamiro Susin, Igor Reis, and Fabiano Hessel, “Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique,” Proc. of Conference on Design, Automation & Test in Europe (DATE), pp. 502-507, Mar. 2005. [8] Tao Yang and Apostolos Gerasoulis, “DSC: Scheduling Parallel Tasks on an Unbounded Number of Processors,” Trans. Parallel and Distributed Systems, vol. 5, no. 9, pp. 951-967, Sept. 1994. [9] Shekhar Borkar, “Thousand core chips – a technology perspective,” Proc. of Design Automation Conference (DAC), pp. 746-749, Jun. 2007. [10] Haluk Topcuoglu, Salim Hariri, and Min-You Wu, “Performance-Effective and Low-Complexity Task Scheduling for Heterogeneous Computing,” IEEE Trans. Parallel and Distributed Systems, vol. 13, no. 3, pp. 260-274, Mar. 2002. [11] Roldan Pozo, Performance Modeling of Sparse Matrix Method for Distributed Memory Architecture, Springer Berlin/Heidelberg, 1st Edition, 1992. [12] Jingcao Hu and Radu Marculescu, “Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures under Real-Time Constraints,” Proc. of Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 234-239, Feb. 2004. [13] Michael Garey and David Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W H Freeman & Co, 1979. [14] Robert Dick, David Rhodes, and Wayne Wolf, “TGFF: Task Graph for Free,” Proc. of Hardware/Software Codesign (CODES/CASHE), pp. 97-101, Mar. 1998. [15] Robert Dick, “Embedded System Synthesis Benchmark Suites (E3S),”: http://ziyang.eecs.umich.edu/~dickrp/e3s/, accessed Jan. 2009. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/22911 | - |
| dc.description.abstract | 本文針對雙向晶片網路架構(bi-dirctional NoC)提出一個效能感知程序映射演算架構,包含程序叢集(task clustering)及程序映射(task mapping)兩個演算法。利用雙向晶片網路架構的資料傳送通道可被調控之特性,在各個時間點分配通道給需要的資料流,以達到提升系統效能之效果。實驗結果顯示本文所提出之效能感知程序映射演算架構可有效降低系統之執行時間,提升系統在雙向晶片網路架構上之效能。 | zh_TW |
| dc.description.abstract | In this Thesis, we propose a performance-aware task mapping algorithm for BiNoC (bi-directional network-on-chip) architecture. The whole framework contains two phases: task clustering and task mapping. For a given task graph and a BiNoC topology, the task clustering phase partitions a task graph into appropriate clusters to minimize the system parallelization time. The task mapping phase employs an SA-based (simulated annealing-based) algorithm which maps clusters of TCG (task communication graph) to PEs (processing elements) injectively. The SA-based algorithm uses real execution time as the cost function and considers the negative effect caused by contentions. Since the channel direction is configurable in a BiNoC, our approach makes use of this characteristic to allocate channel admission to the communication demands and lead to a low system execution time. Experimental results show that, compared to other existing mapping approaches for performance-aware purpose, our approach achieves a significant decrease in packet latency. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T04:33:12Z (GMT). No. of bitstreams: 1 ntu-98-R96943123-1.pdf: 1207562 bytes, checksum: 2e5f024d21536ab886bf7f4898362812 (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | 中文摘要及各章摘要目錄:
目 錄 第一章 簡介 伍 第二章 先行知識 陸 第三章 相關研究 柒 第四章 問題定義 捌 第五章 雙向晶片網路架構之效能感知程序映射 玖 第六章 實驗結果 壹拾 第七章 結論 壹拾壹 英文目錄: ABSTRACT i LIST OF FIGURES v LIST OF TABLES vii CHAPTER 1 INTRODUCTION 1 1.1 Motivation 1 1.2 Objectives 2 1.3 Thesis Organization 2 CHAPTER 2 PRELIMINARIES 3 2.1 Traditional NoC Architecture 3 2.2 Bi-directional NoC Architecture 4 2.3 Task Scheduling 6 2.4 Task Mapping 8 CHAPTER 3 RELATED WORK 11 3.1 Task Scheduling Algorithm 11 3.2 Task Mapping Algorithm 12 3.3 Contributions 14 CHAPTER 4 PROBLEM FORMULATION 17 4.1 Definitions 17 4.2 Time Model 18 CHAPTER 5 PERFORMANCE-AWARE TASK MAPPING FOR BINOC 21 5.1 Methodology 21 5.2 Task Clustering Algorithm 23 5.3 Task Mapping Algorithm 31 CHAPTER 6 EXPERIMENTAL RESULTS 41 6.1 Experiments Setup 41 6.2 Experimental Results 41 CHAPTER 7 CONCLUSION 47 REFERENCE 49 | |
| dc.language.iso | en | |
| dc.subject | 雙向晶片網路架構 | zh_TW |
| dc.subject | 映射 | zh_TW |
| dc.subject | 晶片網路架構 | zh_TW |
| dc.subject | bi-directional NoC | en |
| dc.subject | mapping | en |
| dc.subject | NoC | en |
| dc.subject | BiNoC | en |
| dc.title | 雙向晶片網路架構之效能感知程序映射 | zh_TW |
| dc.title | Performance-aware Task Mapping for Bi-directional NoC Architecture | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 郭斯彥(Sy-Yen Kuo),熊博安(Pao-Ann Hsiung),楊佳玲(Chia-Lin Yang) | |
| dc.subject.keyword | 雙向晶片網路架構,晶片網路架構,映射, | zh_TW |
| dc.subject.keyword | bi-directional NoC,BiNoC,NoC,mapping, | en |
| dc.relation.page | 50 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2009-08-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位: | 電子工程學研究所 | |
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|---|---|---|---|
| ntu-98-1.pdf 未授權公開取用 | 1.18 MB | Adobe PDF |
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