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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林宗賢(Tsung-Hsien Lin) | |
| dc.contributor.author | Yu-Hsiang Huang | en |
| dc.contributor.author | 黃昱翔 | zh_TW |
| dc.date.accessioned | 2021-06-08T04:32:00Z | - |
| dc.date.copyright | 2009-10-05 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-09-23 | |
| dc.identifier.citation | [1] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2000.
[2] B. Zhang, “A 2.4 GHz low power, fully integrated CMOS frequency synthesizer for wireless communications,” Ph.D. dissertation, Georgia Institute of Technology, Atlanta, 2001. [3] F. M. Gardner, “Charge-pump phase-lock loops,” IEEE Trans. Cammun., vol. COM-28, pp. 1849-1858, Nov. 1980. [4] M. Van Paemel, “Analysis of a charge-pump PLL: a new model,” IEEE Transactions on Communications, vol.42, iss.7, July 1994, Page(s): 2490 –2498. [5] M. Bayer, T. Chomicz, F. James, P. McEntarfer, D. Mijuskovic, J. Porter, “A low noise CMOS frequency synthesizer with dynamic bandwidth control,” Proceedings CICC, pp. 8.5.1-8.5.4,1994 [6] C. Vaucher, “An adaptive PLL tuning system architecture combining high spectral purity and fast settling time,” IEEE J. Solid-State Circuits, vol.35, pp. 490-502, Apr. 2000. [7] C.-Y. Yang and S.-I. Liu, “Fast-switching frequency synthesizer with a discriminator-aided phase detector,” IEEE J. Solid-State Circuits, vol. 35, pp. 1445-1452, Oct. 2000. [8] W.-H. Chiu, T.-S. Chang, and T.-H. Lin, “A 5.5-GHz 16-mW fast-locking frequency synthesizer in 0.18-μm CMOS,” IEEE A-SSCC, pp. 456-459, Nov. 2007. [9] B. Memmler, E. Gotz, and G. Schonleber, “New fast-lock PLL for mobile GSM GPRS applications,“ IEEE ESSCIRC, pp. 468-471, Sept. 2000. [10] K. Woo, Y. Liu, E. Nam, D. Ham, “Fast-lock hybrid PLL combining fractional- N and integer-N modes of differing bandwidths,” IEEE J. Solid-State Circuits, vol. 43, pp. 379–389, Feb. 2008. [11] T.-H. Chien, C.-S. Lin, Y.-Z. Juang, C.-M. Huang, C.-L. Wey, “An edge-missing compensator for fast-settling wide-locking-range PLLs, “ISSCC Dig. Tech. Papers, pp. 394-395, Feb. 2009. [12] X. F. Kuang and N. J. Wu, “A fast-settling PLL frequency synthesizer with direct frequency presetting,” ISSCC Dig. Tech. Papers, pp. 741-742, Feb. 2006. [13] S. Shin, K. Lee, and S.-M Kang, “4.2mW CMOS frequency synthesizer for 2.4GHz ZigBee application with fast settling time Performance,” Microwave Symposium Digest, pp. 411-414, June. 2006. [14] W.-H. Chiu, Y.-H. Huang, and T.-H. Lin, “A 5GHz phase-locked loop using dynamic phase-error compensation technique for fast settling in 0.18-μm CMOS,” IEEE Symposium on VLSI circuits, pp. 128-129, June 2009. [15] John Dorsey, Continuous and Discrete Control Systems, Mc Graw Hill. [16] T.-H. Lin, C.-L. Ti, and Y.-H. Liu, “Dynamic current-matching charge pump and gated-offset linearization technique for delta-sigma fractional-N PLLs,” IEEE Trans. Circuits Syst. - I, vol. 56, pp. 877-885, May 2009. [17] B. Razavi, Design of Integrated Circuits for Optical Communications, New York: McGraw-Hill, pp. 341–349, 2003. [18] T.-H. Lin and Y.-J. Lai, “An agile VCO frequency calibration technique for a 10-GHz CMOS PLL,” IEEE J. Solid-State Circuits, vol. 42, pp. 340-349, Feb. 2007. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/22883 | - |
| dc.description.abstract | 本篇論文實現了一個快速鎖定的鎖相迴路。藉由我們所提出的方法，鎖相迴路於鎖定期間，其相位誤差的大小與極性會持續性地被偵測。接著利用動態改變除數的方式來補償所偵測到的相位誤差。由於在鎖定過程中，鎖相迴路都維持在一個較小的相位誤差。因此，鎖定時間可有效地縮短。除此之外，在此作品內加入了一個輔助性的充電幫浦，提供適當的電流給迴路濾波器以加快頻率的改變速度。此快速鎖定的方法實現於一個50億赫茲的鎖相迴路。使用台積電0.18深次微米製程，整個鎖相迴路操作在1.8-V共花費11mA電流。所量測到的鎖定時間為2us於40-kHz的迴路頻寬下。在53.4億赫茲下，相位雜訊於1-MHz頻率誤差下為-114.28 dBc/Hz，參考頻率突波於10-MHz頻率誤差下低於-70 dBc。 | zh_TW |
| dc.description.abstract | This thesis presents a fast-locking technique for phase-locked loops (PLLs). In the proposed technique, the polarity and magnitude of the phase error at the phase-frequency detector (PFD) input is continuously monitored during the locking process. The detected phase error is then coarsely compensated by dynamically changing the divide ratios. The proposed method allows the PLL to maintain a small phase error throughout the frequency acquisition process; thereby reducing settling time. To further enhance the locking speed, an auxiliary charge pump is applied to the loop filter during the fast-locking mode to facilitate a rapid frequency update.
The proposed technique is incorporated in the design of a 5-GHz PLL. Fabricated in the TSMC 0.18-μm CMOS technology, the whole PLL dissipates 11 mA from a 1.8-V supply. The measured settling time is about 2μs at a 40-kHz steady-state loop bandwidth. At 5.34 GHz, the phase noise measured at 1-MHz offset is -114.28 dBc/Hz, and the reference spurs at 10-MHz offset are lower than -70 dBc. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T04:32:00Z (GMT). No. of bitstreams: 1 ntu-98-R96943025-1.pdf: 1833566 bytes, checksum: b81c4ef0b7b21c449563cfd12163f818 (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | Chapter 1 Introduction 1
1.1 Motivation 1 1.2 Thesis Overview 2 Chapter 2 Introduction to Phase-Locked Loops 3 2.1 The operation principle of a PLL 3 2.2 The Basics of PLL Building Blocks and Modeling 4 2.2.1 Phase Frequency Detector (PFD) and Charge Pump (CP) 5 2.2.2 Voltage-Controlled Oscillator (VCO) 6 2.2.3 Frequency Divider (FD) 7 2.3 Design Issues and System Analysis of A PLL 9 2.4 Dynamics behavior Analysis of A PLL 12 2.5 Summary 13 Chapter 3 Fast-Locking PLL Using Dynamic Phase-Error Compensation Technique 15 3.1 Introduction 15 3.1.1 Background 15 3.1.2 Methods to improve settling speed of PLL 16 3.2 Principle of the Proposed Fast-Settling Method 19 3.3 Proposed Fast-Locking Architecture and Implementation 20 3.3.1 Architecture Implementation 21 3.4 Linear Model of Proposed Architecture 24 3.4.1 Linear Model of 3-stage DAPD 25 3.4.2 Linear Model of Auxiliary Charge Pump 27 3.4.3 Linear Model of phase compensation 27 3.4.4 Linear Model of Proposed PLL Structure 28 3.4.5 Stability Analysis 31 3.4.6 Transient Behavior of Proposed PLL Structure 32 3.4.7 Design Parameters Calculation 34 3.4.8 Design example and comparison 35 3.5 Implementation of a 5GHz Fast-Settling PLL 40 3.5.1 PFD and Charge Pump 41 3.5.2 3-Stage DAPD 44 3.5.3 Auxiliary Charge Pump 45 3.5.4 Dynamic Adjustable Divider Chain 47 3.5.5 Voltage-Controlled Oscillator 51 3.6 Fast-locking PLL system Simulation 54 3.6.1 Behavior System Simulation 54 Chapter 4 Experimental Results 59 4.1 Test Environment Setup 59 4.2 Chip Pin Configurations and Printed Circuit Board Design 60 4.2.1 Chip Pin Configurations 60 4.2.2 Printed Circuit Board Design 61 4.3 The DC supply Regulator 63 4.4 Experimental Results 63 4.4.1 Fast-locking PLL transient measurement results 64 4.4.2 Comparison of Fast-locking PLL and Bandwidth switching PLL 67 4.4.3 Phase noise and reference spur measurement results 68 4.5 Summary of Measured Results 70 Chapter 5 Conclusions and future work 71 5.1 Conclusions 71 5.2 Future work 71 References 73 | |
| dc.language.iso | en | |
| dc.title | 利用動態相位誤差補償技巧之快速鎖定鎖相迴路 | zh_TW |
| dc.title | A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李泰成(Tai-Cheng Lee),呂良鴻(Liang-Hung Lu) | |
| dc.subject.keyword | 鎖相迴路,快速鎖定,相位補償,頻率合成器, | zh_TW |
| dc.subject.keyword | PLL,fast-locking,phase error compensation,frequency synthesizer, | en |
| dc.relation.page | 76 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2009-09-23 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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