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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 林宗賢(Tsung-Hsien Lin) | |
dc.contributor.author | Chien-Yuan Cheng | en |
dc.contributor.author | 程健源 | zh_TW |
dc.date.accessioned | 2021-06-08T04:31:48Z | - |
dc.date.copyright | 2009-10-05 | |
dc.date.issued | 2009 | |
dc.date.submitted | 2009-09-29 | |
dc.identifier.citation | [1]U. L. Rohde, RF and microwave digital frequency synthesizer, Wiley, New York, 1997.
[2]C. A. Kingsford-Smith, Patent No. 3,928,813, Washington DC: US Patent Office, 1975. [3]D. Bufferfield, and B. Sun, “Prediction of fractional-N spurs for UHF PLL frequency synthesizers,” IEEE MTT-S Symposium on Technologies for Wireless Applications Tech. Dig., pp. 29-34, Feb. 1999. [4]E. Temporiti, G. Albasini, I. Bietti, R. Castello, and M. Colombo, “A 700-kHz bandwidth fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1446-1454, Sep. 2004. [5]C. Y. Yang, and S. I. Liu, “Fast-switching frequency synthesizer with a discriminator-aided phase detector,” IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1445-1452, Oct. 2000. [6]T. A. Riley, M. A. Copeland, and T. A. Kwasniewski, “Delta-sigma modulation in fractional-N frequency synthesis,” IEEE J. Solid-State Circuits, vol. 28, no. 5, pp. 553-559, May 1993. [7]S. E. Meninger, and M. H. Perrott, “A fractional-N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise,” IEEE Trans. Circuits Syst. -II, vol. 50, no. 11, pp. 839-849, Nov. 2003. [8]S. Pamarti, L. Jansson, and I. Galton, “A wideband 2.4-GHz delta-sigma fractional-N PLL with 1-Mb/s in-loop modulation,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 49-62, Jan. 2004. [9]A. Swaminathan, K. J. Wang, and I. Galton, “A wide-bandwidth 2.4 GHz ISM band fractional-N PLL with adaptive phase noise cancellation,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2639-2650, Dec. 2007. [10]T.-C. Lee, and B. Razavi, “A stabilization technique for phase-locked frequency synthesizers,” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 888-894, June 2003. [11]W.-H. Chiu, T.-S. Chan, and T.-H. Lin, “A 5.5-GHz 16-mW fast-locking frequency synthesizer in 0.18-um CMOS,” IEEE Asian Solid-State Circuits Conference, pp. 456-459, Nov. 2007. [12]B. D. Muer, and M. S. J. Steyaert, “A CMOS monolithic DS-controlled fractional-N frequency synthesizer for DCS-1800,” IEEE J. Solid-State Circuits, vol. 37, no. 7, pp. 835-844, July 2002. [13]W. S. T. Yan, and H. C. Luong, “A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers,” IEEE J. Solid-State Circuits, vol. 36, pp. 204-216, 2001. [14]K. Arshak, O. Abubaker, and E. Jafer, “Design and simulation difference type CMOS phase frequency detector for high speed and low jitter PLL,” Proceeding of 15th IEEE International Caracas Conference on Devices, Circuits and Systems, vol. 1, pp. 188-191, Nov. 2004. [15]W. -H. Lee, J. -D. Cho, and S. -D. Lee, “A high speed and low power phase-frequency detector and charge-pump,” Proceedings of the Asia and South Pacific Design Automation Conference, vol. 1, pp. 269-272, Jan. 1999. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/22878 | - |
dc.description.abstract | 在無線通訊系統中,頻率合成器扮演重要的角色,無論是發射機、傳輸機,都需要頻率合成器來產生本地震盪頻率。而且,發射機之實現也可單獨藉由在鎖相迴路式頻率合成器之迴路內部調變來達成。在控制除數來調變壓控振盪器的方式中,雖然擁有較低的能量消耗和較少的電路元件,但頻率合成器的迴路頻寬限制了發射機的資料傳輸率。所以如何增加頻率合成器的頻寬是本論文主要探討的課題。
在本論文中,提出了一個新的電路方法,稱為相關相位消除技術。使用一個除頻器陣列來產生相關相位。兩組電流幫浦可由數位訊號來控制電流比例,然後消除相關相位。沒有被如三角積分調變架構頻率合成器出現的量化誤差雜訊所困擾,所以能夠達到較寬的迴路頻寬。最後,量測結果顯示,此頻率合成器鎖定在4.8-GHz,並且在100-kHz之迴路頻寬、參考頻率為25-MHz之條件下,達到-49 dBc的小數突波。此時,整個頻率合成器功率消耗在1.2 V的電壓供應之下花了17毫瓦。 | zh_TW |
dc.description.abstract | A frequency synthesizer plays an important role in wireless communication system. Both transmitter and receiver need the synthesizer to generate local oscilation frequency. In addition, a transmitter can be implemented by utilizing the in-loop modulation of a phase-locked loop (PLL) based frequency synthesizer. In the technique of indirectly modulating the VCO by varying the divide value, although it has lower power consumption and less circuit components, the transmitter’s transmission data rate is restricted within the loop bandwidth of frequency synthesizer. Thus, widening the loop bandwidth can be a challenging design problem in this thesis.
In the thesis, a new approach is called “relative-phase cancellation” (RPC) technique. The relative phase is made a divider array, and the charge pump current ratio is controlled by digital code. Thus, the relative phase can be cancelled. The RPC technique can achieve wide bandwidth, because there is no quantization noise which appears in delta-sigma fractional-N frequency synthesizer. Finally, the measurement results reveal that the RPC frequency synthesizer is locked at 4.7-GHz, and it achieves a magnitude of -49 dBc fractional spurs with a 100-kHz loop bandwidth and a 25-MHz reference frequency. The measured power consumption with a 1.2-V supply voltage is about 17 mW. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T04:31:48Z (GMT). No. of bitstreams: 1 ntu-98-R96943132-1.pdf: 4676767 bytes, checksum: 68e8095408ed9e408c58c28c0f993377 (MD5) Previous issue date: 2009 | en |
dc.description.tableofcontents | Chapter 1 Introduction 1
1.1 Motivation 1 1.2 Thesis Overview 3 Chapter 2 Fundamentals of Fractional-N Frequency Synthesizer 5 2.1 Frequency Synthesizer Basics and Modeling 5 2.1.1 Voltage-Controlled Oscillator 7 2.1.2 Frequency Divider 8 2.1.3 Phase Frequency Detector and Charge Pump 9 2.2 Fractional-N Frequency Synthesizer 10 2.3 Design Issues and Analysis of a Frequency Synthesizer 13 2.4 Fractional Spur Analysis 15 2.5 Summary 19 Chapter 3 Relative-Phase Cancellation Fractional-N Frequency Synthesizer 21 3.1 Introduction 21 3.2 Background and Issues 21 3.3 Implementation of Relative-Phase Cancellation Fractional-N Frequency Synthesizer 25 3.3.1 System Architecture 27 3.3.2 Major Building Block of the Frequency Synthesizer 29 3.3.2.1 Divider Array 29 3.3.2.2 Charge Pump Array 33 3.3.2.3 PFD 36 3.3.2.4 Sampling Loop Filter 41 3.3.2.5 Voltage-Controlled Oscillator 43 3.3.3 Other Building Block of the Frequency Synthesizer 48 3.3.3.1 Delta-Sigma Modulator 48 3.4 Simulation Results 49 3.4.1 Behavior System Simulation 49 3.4.2 Transistor-Level System Simulation 51 Chapter 4 Measurement 53 4.1 Test Environment Setup 53 4.2 Chip Floor Plan and PCB Design 55 4.3 Measurement Results 58 4.4 Performance Summary 61 Chapter 5 Conclusions and Future Work 63 5.1 Conclusions 63 5.2 Future Work 64 Bibliography 65 | |
dc.language.iso | en | |
dc.title | 俱相關相位消除技巧之5-GHz小數型頻率合成器 | zh_TW |
dc.title | Design of a 5-GHz Relative-Phase Cancellation Fractional-N Frequency Synthesizer | en |
dc.type | Thesis | |
dc.date.schoolyear | 98-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 呂良鴻(Liang-Hung Lu),李泰成(Tai-Cheng Lee) | |
dc.subject.keyword | 鎖相迴路,相關相位,除小數,頻率合成器, | zh_TW |
dc.subject.keyword | fractional-N,frequency synthesizer,relative-phase cancellation, | en |
dc.relation.page | 66 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2009-09-29 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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