請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/21813
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
dc.contributor.author | Yu-Kai CHIU | en |
dc.contributor.author | 邱鈺凱 | zh_TW |
dc.date.accessioned | 2021-06-08T03:47:58Z | - |
dc.date.copyright | 2019-01-24 | |
dc.date.issued | 2019 | |
dc.date.submitted | 2019-01-21 | |
dc.identifier.citation | [1]Y. C. Huang and S. I. Liu, “A 2.4-GHz subharmonically injection-locked PLL with self-calibrated injection timing,” IEEE J. Solid-State Circuits, vol. 48, no. 11, pp. 417–428, Feb. 2013.
[2]A. Musa et al., “A compact, low-power and low-jitter dual-loop injection locked PLL using all-digital PVT calibration,” IEEE J. Solid-State Circuits, vol. 49, no. 1, pp. 50–60, Jan. 2014. [3]S. Choi, S. Yoo, Y. Lim, and J. Choi, “A PVT-robust and low-jitter ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector,” IEEE J. Solid-State Circuits, vol. 51, no. 8, pp. 1878–1889, Aug. 2016. [4]Y. Lee, H. Yoon, M. Kim, and J. Choi, “A PVT-robust −59-dBc reference spur and 450-fsRMS jitter injection-locked clock multiplier using a voltage-domain period-calibrating loop,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp. 238–239, June 2016. [5]B. M. Helal, C. M. Hsu, K. Johnson, and M. H. Perrott, “A low jitter programmable clock multiplier based on a pulse injection-locked oscillator with a highly-digital tuning loop,” IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1391–1400, May. 2009. [6]C. W. Tien and S. I. Liu, “A PVT-tolerant injection-locked clock multiplier with a frequency calibrator using a delay time detector,” to be published in IEEE Trans. Circuits Syst. II, Express Briefs. [7]C. H. Chiang, C. C. Huang, T. K. Kuan, and S. I. Liu. “A digital MDLL using switched biasing technique to reduce low-frequency phase noise,” in Proc. A-SSCC, pp. 101-104, Nov. 2016 [8]S. Yang, J. Yin, P. Mak and R. P. Martins, “A 0.0056-mm² -249-dB-FoM all-digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs,” in IEEE ISSCC Dig. Tech. Papers, pp. 118–119, Feb. 2018. [9]T. A. Ali, A. A. Hafez, R. Drost, R. Ho, and C. K. K. Yang, “A 4.6 GHz MDLL wth 46 dBc reference spur and aperture position tuning,” in IEEE ISSCC Dig. Tech. Papers, pp. 466–468, Feb. 2011. [10]S. Levatino, G. Marucci, G. Marzin, A. Fenaroli, C. Samori, and A. L. Lacaita, “A 1.7 GHz fractional-N frequency synthesizer based on a multiplying delay-locked loop,” IEEE J. Solid-State Circuits, vol. 50, no. 11, pp. 2678–2691, Nov. 2015. [11]B. M. Helal, M. Z. Straayer, G.Y. Wei, and M. H. Perrott, “A highly digital MDLL-based clock multiplier that leverages a self-scrambling time-to-digital converter to achieve subpicosecond jitter performance,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 855–863, Apr. 2008. [12]H. Kim, Y. Kim, T. Kim, H. Ko, and S. Cho, “A 2.4-GHz 1.5-mW digital multiplying delay-locked loop using pulse-width comparator and double injection technique,” IEEE J. Solid-State Circuits, vol. 52, no. 11, pp. 2934–2946, Nov. 2017. [13]A. Elshazly, B. Young, and P. K. Hanumolu, “Clock multiplication techniques using digial multiplying delay-locked loops,” IEEE J. Solid-State Circuits, vol. 48, no. 6, pp. 1416–1428, June 2013. [14]S. Kubdu, B. Kim, and C. Kim, “A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection,” IEEE J. Solid-State Circuits, vol. 48, no. 6, pp. 799–810, June 2017. [15]D-N Jhou, W-S Chang, and T-C Lee, “A 5.12-GHz Fractional-N clock multiplier with an LC-VCO-based MDLL,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp. 132–133, June 2017. [16]S. Ye et al., “A multiple-crystal interface PLL with VCO realignment to reduce phase noise,” in IEEE ISSCC Dig. Tech. Papers, pp. 58–401, Feb. 2002. [17]X. Gao, E. Klumperink, M. Bohsali, and B. Nauta, “A low-noise subsampling PLL in which divider noise is eliminated and PD/CP noise is not multiplied by N2,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3253–3263, Dec. 2009. [18]X. Gao, E. Klumperink, and B. Nauta, “Sub-sampling PLL techniques,” in Proc. IEEE Custom Integr. Circuits Conf. (CICC), San Jose, CA, USA, pp. 1–8, Sep. 2015. [19]J. Shin and H. Shin, “A fast and high-precision VCO frequency calibration technique for wideband fractional-N frequency synthesizers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 7, pp. 1573–1582, July 2010. [20]J. Zhu, R. Nandwana, G. Shu, A. Elkholy, S.-J. Kim, and P. Hanumolu, “A 0.0021 mm2 1.82 mW 2.2 GHz PLL using time-based integral control in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 52, no. 1, pp. 8–20, Jan. 2017. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/21813 | - |
dc.description.abstract | 本論文實現一具製程、溫度與電壓背景校正之倍頻延遲鎖定迴路,為了降低參考突波與相位抖動,本論文提出一具延遲校正之次取樣相位偵測器來校正頻率誤差,其中相位偵測器與電荷泵的相位雜訊不會被放大N2倍,為了增加迴路的頻率涵蓋與降低製程、溫度與電壓所造成的非理想效應,本論文也提出一背景執行之頻率選擇器,本論文已於台積電40奈米製程實踐與驗證,本電路輸出時脈為2.4GHz,其輸入參考頻率為150MHz,電路佈局面積為0.0135 mm2,於1V之工作電壓下,總功率消耗為5.2mW,量測之方均根抖動量為229fs,參考突波為-54.3dBc。 | zh_TW |
dc.description.abstract | A multiplying delay-locked loop (MDLL) with a background coarse-frequency selector and a frequency calibrator is presented. To reduce the reference spur due to the frequency error, a frequency calibrator using a delay-calibrated SSPD is presented. The phase noise of the CP and the SSPD is not multiplied by N2. To cover a wide frequency variation, the background coarse-frequency selector is also presented. This MDLL is fabricated in 40-nm CMOS technology. The active area is 0.013mm2, and the power consumption is 5.2mW from a supply of 1V. It exhibits a root-mean-square jitter of 229fs at 2.4GHz output and the reference spur of -54.3dBc under a reference clock of 150MHz. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T03:47:58Z (GMT). No. of bitstreams: 1 ntu-108-R05943131-1.pdf: 4386223 bytes, checksum: 16f54d11e67c7b16ccd6ffb361a40130 (MD5) Previous issue date: 2019 | en |
dc.description.tableofcontents | 1. Introduction-1
1.1 Motivation-1 1.2 Overview-2 2. A PVT-Tolerant MDLL with a Background Coarse- Frequency Selector and a Frequency Calibrator-4 2.1 Problem Analysis-4 2.2 Circuit Description-7 2.2.1 MDLL-7 2.2.2 Reference Buffer and Select Logic-9 2.2.3 Frequency Calibrator-10 2.2.4 Background CFS-14 2.2.5 Voltage-Controlled Oscillator (VCO) and Dummy Block-18 2.3 Linear model analysis-20 2.3.1 Stability-23 2.3.2 Phase Noise Calculated Result-25 3. Experimental Results-30 3.1 Measurement Results-30 3.2 Performance Summary-38 4. Conclusion and Future Work-39 4.1 Conclusion-39 4.2 Future Work-40 Bibliography-41 | |
dc.language.iso | en | |
dc.title | 具製程、電壓與溫度背景校正之倍頻延遲鎖定迴路 | zh_TW |
dc.title | A PVT-Tolerant MDLL with a Background Coarse-Frequency Selector and a Frequency Calibrator using a Delay-Calibrated SSPD | en |
dc.type | Thesis | |
dc.date.schoolyear | 107-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 李泰成(Tai-Cheng Lee),林宗賢(Tsung-Hsien Lin),鄭國興(Kuo-Hsing Cheng),楊清淵(Ching-Yuan Yang) | |
dc.subject.keyword | 鎖相迴路,倍頻延遲鎖定迴路,頻率合成器, | zh_TW |
dc.subject.keyword | Phase-Locked Loop,Multiplying Delay-Locked Loop,Frequency Synthesizer, | en |
dc.relation.page | 51 | |
dc.identifier.doi | 10.6342/NTU201900154 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2019-01-22 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-108-1.pdf 目前未授權公開取用 | 4.28 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。