25-Gb/s不歸零碼接收器之設計

Abstract

隨著通訊系統對資料傳送速率的要求越來越高，100-Gb/s乙太網路系統將開始全面普及，作為乙太網路的重要組成部分，高速接收器電路顯得尤為關鍵，本論文中提出25-Gb/s NRZ接收端，包含了可變增益放大器、限幅放大器、連續時間等化器、自適應的四抽頭決斷反饋等化器、基於相位內插器的全數位時脈資料恢復電路，以及具有三個抽頭前饋式等化器的輸出級電路。 25-Gb/s NRZ接收器在量測上達到在奈奎斯特頻率有11.5dB損耗的輸入資料下仍能恢復出無誤碼(BER<〖10〗^(-12))的全速資料，以及具有輸入資料為50mV擺幅時輸出仍能達到無誤碼的靈敏度，全數位時脈資料恢復電路的抖動容忍度也優於IEEE 802.3的標準，時脈資料恢復電路的迴路頻寬在量測上達到了2MHz到10MHz可調，並且在輸入資料具有100MHz的正弦抖動時電路仍能有0.48UIp-p的抖動振幅容忍度(BER<〖10〗^(-12))，另外基於相位內插器的時脈資料恢復電路具有-720ppm ~ +1120ppm的頻差容忍度，而三個抽頭的前饋式等化器在量測上也達到了將近8dB的補償量，輸出級可將輸出訊號擺福在200mV~800mV之間透過控制碼進行調整，量測上電路即便到28Gb/s、以及30Gb/s的輸入仍能正常運作順利恢復出資料。

The data transmission speed is getting faster and faster in communication system nowadays, 100-Gb/s Ethernet system will be popular. As an important part of the Ethernet system, high-speed receiver circuits are especially critical. In this thesis, a 25-Gb/s NRZ receiver is proposed, which includes a variable gain amplifier, a limiting amplifier, a continuous time linear equalizer, an adaptive 4-tap decision feedback equalizer, a phase interpolator-based full digital clock and data recovery circuit and an output driver with a three-tap feedforward equalizer. On the measurement, 25-Gb/s NRZ receiver can recover the input with 11.5dB loss to the error-free (BER < 〖10〗^(-12)) data output, and with the sensitivity that output can be achieved error-free (BER<〖10〗^(-12)) under 50mV input swing. The jitter tolerance of the all-digital clock and data recovery circuit is better than the IEEE 802.3 standard. The loop bandwidth of CDR on measurement can be adjusted from 2MHz to 10MHz, and the CDR can still have 0.48 UIp-p jitter amplitude tolerance when the input data has 100MHz sinusoidal jitter. PI-based CDR has a frequency tolerance of -720ppm ~ +1120ppm. The three-tap feedforward equalizer also achieves nearly 8-dB boosting in measurement, and the output swing can be controlled between 200mV~800mV. The receiver can recover the data even after the input up to 28-Gb/s and 30-Gb/s.