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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 吳肇欣(Chao-Hsin Wu) | |
dc.contributor.author | Ang-Kuan Chen | en |
dc.contributor.author | 陳昂寬 | zh_TW |
dc.date.accessioned | 2021-06-08T03:31:48Z | - |
dc.date.copyright | 2019-08-19 | |
dc.date.issued | 2019 | |
dc.date.submitted | 2019-08-12 | |
dc.identifier.citation | 1. Skotnicki, T., et al., The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance. IEEE Circuits and Devices Magazine, 2005. 21(1): p. 16-26.
2. Seabaugh, A.C. and Q. Zhang, Low-Voltage Tunnel Transistors for Beyond CMOS Logic. Proceedings of the IEEE, 2010. 98(12): p. 2095-2110. 3. Appenzeller, J., et al., Band-to-Band Tunneling in Carbon Nanotube Field-Effect Transistors. Physical Review Letters, 2004. 93(19): p. 196805. 4. Ionescu, A.M. and H. Riel, Tunnel field-effect transistors as energy-efficient electronic switches. Nature, 2011. 479: p. 329. 5. Krishnamohan, T., et al. Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and ≪60mV/dec subthreshold slope. in 2008 IEEE International Electron Devices Meeting. 2008. 6. Yoon, Y. and S. Salahuddin, Barrier-free tunneling in a carbon heterojunction transistor. Applied Physics Letters, 2010. 97(3): p. 033102. 7. Gopalakrishnan, K., P.B. Griffin, and J.D. Plummer, Impact ionization MOS (I-MOS)-Part I: device and circuit simulations. IEEE Transactions on Electron Devices, 2005. 52(1): p. 69-76. 8. Gopalakrishnan, K., et al., Impact ionization MOS (I-MOS)-Part II: experimental results. IEEE Transactions on Electron Devices, 2005. 52(1): p. 77-84. 9. Salahuddin, S. and S. Datta, Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices. Nano Letters, 2008. 8(2): p. 405-410. 10. Liu, F., et al., Negative capacitance transistors with monolayer black phosphorus. Npj Quantum Materials, 2016. 1: p. 16004. 11. McGuire, F.A., et al., Sustained Sub-60 mV/decade Switching via the Negative Capacitance Effect in MoS2 Transistors. Nano Letters, 2017. 17(8): p. 4801-4806. 12. Qiu, C., et al., Dirac-source field-effect transistors as energy-efficient, high-performance electronic switches. 2018. 361(6400): p. 387-392. 13. Liu, F., et al., Dirac Electrons at the Source: Breaking the 60-mV/Decade Switching Limit. IEEE Transactions on Electron Devices, 2018. 65(7): p. 2736-2743. 14. Chang, H.-M., et al., Germanium-doped Metallic Ohmic Contacts in Black Phosphorus Field-Effect Transistors with Ultra-low Contact Resistance. Scientific Reports, 2017. 7(1): p. 16857. 15. Koenig, S.P., et al., Electric field effect in ultrathin black phosphorus. Applied Physics Letters, 2014. 104(10): p. 103106. 16. Yang, J., P. Hu, and G. Yu, Perspective of graphene-based electronic devices: Graphene synthesis and diverse applications. APL Materials, 2019. 7(2): p. 020901. 17. Ganatra, R. and Q. Zhang, Few-Layer MoS2: A Promising Layered Semiconductor. ACS Nano, 2014. 8(5): p. 4074-4099. 18. Radisavljevic, B., et al., Single-layer MoS2 transistors. Nature Nanotechnology, 2011. 6: p. 147. 19. Li, X. and H. Zhu, Two-dimensional MoS2: Properties, preparation, and applications. Journal of Materiomics, 2015. 1(1): p. 33-44. 20. Watanabe, K., T. Taniguchi, and H. Kanda, Direct-bandgap properties and evidence for ultraviolet lasing of hexagonal boron nitride single crystal. Nature Materials, 2004. 3: p. 404. 21. Giovannetti, G., et al., Substrate-induced band gap in graphene on hexagonal boron nitride: Ab initio density functional calculations. Physical Review B, 2007. 76(7): p. 073103. 22. Petrone, N., et al. Flexible 2D FETs using hBN dielectrics. in 2015 IEEE International Electron Devices Meeting (IEDM). 2015. 23. Young, A.F., et al., Electronic compressibility of layer-polarized bilayer graphene. Physical Review B, 2012. 85(23): p. 235458. 24. Andres, C.-G., et al., Deterministic transfer of two-dimensional materials by all-dry viscoelastic stamping. 2D Materials, 2014. 1(1): p. 011002. 25. Pizzocchero, F., et al., The hot pick-up technique for batch assembly of van der Waals heterostructures. Nature Communications, 2016. 7: p. 11894. 26. Liu, Y., et al., Toward Barrier Free Contact to Molybdenum Disulfide Using Graphene Electrodes. Nano Letters, 2015. 15(5): p. 3030-3034. 27. Kim, H.G. and H.-B.-R. Lee, Atomic Layer Deposition on 2D Materials. Chemistry of Materials, 2017. 29(9): p. 3809-3826. 28. Yang, W., et al., The Integration of Sub-10 nm Gate Oxide on MoS2 with Ultra Low Leakage and Enhanced Mobility. Scientific Reports, 2015. 5: p. 11921. 29. Zhang, E., et al., Tunable Charge-Trap Memory Based on Few-Layer MoS2. ACS Nano, 2015. 9(1): p. 612-619. 30. Datta, S., Quantum Transport: Atom to Transistor Cambridge, UK: Cambridge Univ. Press, 2005. 31. Britnell, L., et al., Field-Effect Tunneling Transistor Based on Vertical Graphene Heterostructures. Science, 2012. 335(6071): p. 947-950. 32. Choi, K., et al., Trap density probing on top-gate MoS2 nanosheet field-effect transistors by photo-excited charge collection spectroscopy. Nanoscale, 2015. 7(13): p. 5617-5623. 33. Zhao, P., et al., Evaluation of border traps and interface traps in HfO2/MoS2 gate stacks by capacitance–voltage analysis. 2D Materials, 2018. 5(3): p. 031002. 34. Wang, Z., et al., The ambipolar transport behavior of WSe2 transistors and its analogue circuits. NPG Asia Materials, 2018. 10(8): p. 703-712. 35. Liu, W., et al., Role of Metal Contacts in Designing High-Performance Monolayer n-Type WSe2 Field Effect Transistors. Nano Letters, 2013. 13(5): p. 1983-1990. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/21351 | - |
dc.description.abstract | 隨著人們對於電子器件功耗的要求日益增加,科學家們持續進行各種嘗試,例如更換材料或是發明新的電晶體架構,使元件的操作電壓降低。狄拉克源(Dirac-source)有別於一般源極材料,其狀態密度與能量呈線性關係。由於這樣的特性,使得狄拉克源在費米能階附近時,具有比傳統材料更窄的電子密度分布,因此讓次臨界擺幅得以突破物理極限之60mV/decade,操作電壓得以有效地下降。
而在本論文中,我們將以二維材料二硫化鉬及二硒化鎢做為通道材料,並結合石墨烯,完成一狄拉克源電晶體。首先,我們先以二硫化鉬做為通道,石墨烯做為源極材料,完成一個二維異質結構電晶體,並與傳統以鈦金做為源極之電晶體進行電性比較。接著,我們以氮化硼(Hexagonal Boron Nitride, h-BN)當作介電層,結合前述之異質結構,完成初版的狄拉克源電晶體。然而,氮化硼之厚度與對準皆不易控制,不適合應用於往後的上閘極元件製作,因此我們改用較常見也較便於製程的原子層沉積 (Atomic layer deposition, ALD)的氧化鋁來當作我們介電層。 然而,由於二維材料表面缺少未鍵結電子對,使得ALD氧化層難以均勻地沉積於材料上。有鑒於此,我們在樣品表面先沉積一層兩奈米厚的種子層(seed layer),成功提升了ALD氧化層的表面品質,亦成功使得上閘極電晶體之開關比達到106。 最後,我們將上閘極介電質的技術,與異質結構電晶體做結合,成功地完成了二硫化鉬及二硒化鎢之狄拉克源電晶體,並看到了次臨界擺幅隨控制閘極之電壓調變而降低的效果,相關的物理機制分析探討亦於內文中詳細介紹。 | zh_TW |
dc.description.abstract | To meet the need for low power devices, scientists have tried their best to find a new channel material or a new device mechanism, to lower the supply voltage of devices. Dirac-source(DS), different from normal source, has a linear DOS as a function of energy, which gives rise to a much narrower electron density distribution around the Fermi level than conventional source. Because of this characteristic, the device with DS can break the subthreshold swing limit of 60mV/decade and therefore has a lower supply voltage.
In this paper, we want to use 2D materials like MoS2 or WSe2 as channel, to fabricate a DS-FET and achieve SS lowering. At the beginning, we will demonstrate graphene-contacted MoS2 back-gate FETs, show the electrical characteristics and compare with Ti-contacted ones. Next, we use hexagonal boron nitride (h-BN) as top-gate dielectric, and combine it with graphene-contacted MoS2 back-gate FET to complete a prototype of DS-FET. However, we find that it is very hard to control the position and thickness of h-BN, so we switch to ALD process to form the top-gate dielectric. Nevertheless, because 2D material lacks of dangling bonds on its surface, we have difficulty forming a uniform ALD Al2O3 film on it. To solve the problem, we evaporate a 2nm E-gun Al2O3 seed layer before ALD process, and successfully improve the quality of the ALD Al2O3 film. We utilize this top-gate dielectric technique to fabricate a 2D top-gate FET with ION/IOFF~106. Finally, we combine top-gate dielectric technique with graphene-contacted MoS2 back-gate FETs, to fabricate MoS2 DS-FET and WSe2 DS-FET. We also complete the measurement and analysis, and the phenomenon of SS lowering is observed with various control-gate biases. Further mechanism and analysis will be introduced in the articles. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T03:31:48Z (GMT). No. of bitstreams: 1 ntu-108-R06943067-1.pdf: 3877201 bytes, checksum: ba8c92c7747091aa7084cb28a8c18fe6 (MD5) Previous issue date: 2019 | en |
dc.description.tableofcontents | 口試委員審定書 I
誌謝 II 摘要 IV Abstract V Table of Contents VII List of Figures X List of Tables XIII Chapter 1. Introduction and Research Motivation 1 1.1 Introduction 1 1.2 Introduction of 2D Materials 4 1.2.1 Graphene 5 1.2.2 Molybdenum Disulfide (MoS2) 6 1.2.3 Hexagonal Boron Nitride (h-BN) 7 1.3 Research Motivation 8 1.4 Organization of Work 9 Chapter 2. Fabrication Process of Hetero-Structure 2D Material Field-Effect Transistors 10 2.1 Preface 10 2.2 Fabrication Process of Basic 2D Material Back-gate Transistor 11 2.2.1 Substrate Preparation 11 2.2.2 Few-layered 2D Material Flakes Exfoliation and Transfer 11 2.2.3 Electron Beam Lithography (EBL) and S/D Metal Deposition 12 2.2.4 Summary of Device Fabrication 15 2.3 Hetero-Structure 2D Material Field-Effect Transistor 18 2.3.1 PDMS Dry Transfer Technique 18 2.4 Discussion of Graphene-contacted MoS2 Back-gate FETs 22 2.5 Summary 27 Chapter 3. Optimization of Top-gate Field-Effect Transistors 28 3.1 Preface 28 3.2 Prototype of Dirac-Source Field-Effect Transistors 29 3.2.1 Process Flow 29 3.2.2 Electrical Characteristics 31 3.3 Top-gate Dieletric Deposition 34 3.3.1 Conventional ALD Al2O3 Process on 2D Materials 34 3.3.2 ALD Al2O3 with Ti seed layer 39 3.3.3 ALD Al2O3 with E-gun Al2O3 seed layer 43 3.4 Summary 48 Chapter 4. MoS2 & WSe2 Dirac-Source Field-Effect Transistors 49 4.1 Preface 49 4.2 MoS2 Dirac-Source Field-Effect Transistors 50 4.2.1 Process Flow and Measurement Setup 50 4.2.2 Electrical Characteristics and Mechanism 54 4.3 WSe2 Dirac-Source Field-Effect Transistors 62 4.3.1 Nickel-contacted WSe2 Field-Effect Transistors 62 4.3.2 Electrical Characteristics and Mechanism 64 Chapter 5. Conclusion and Future Work 69 Reference 71 | |
dc.language.iso | en | |
dc.title | 狄拉克源電晶體開發及研究 | zh_TW |
dc.title | Development and Investigation of Dirac-Source Field-Effect Transistor | en |
dc.type | Thesis | |
dc.date.schoolyear | 107-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 陳建宏,張書維,吳育任,張子璿 | |
dc.subject.keyword | 狄拉克源,次臨界擺幅,石墨烯,二硫化鉬,異質結構,原子層沉積,二硒化鎢,控制閘極, | zh_TW |
dc.subject.keyword | Dirac-source,Subthreshold Swing,Graphene,MoS2,Hetero-structure,Atomic Layer Deposition,WSe2,control-gate, | en |
dc.relation.page | 75 | |
dc.identifier.doi | 10.6342/NTU201902996 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2019-08-12 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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