乙太網路應用之高速收發器

Abstract

本論文提出了兩項作品。第一項作品是原型發射機，具有內置的PRBS-7測試模式和三抽頭前饋均衡器。 在14 GHz時可提供大約8 dB的最大增強。為了通過復用器將不同相位的四個四分之一速率的PRBS序列合成為半速率數據序列，提出了一種改進的2-to-1復用器。沿時鐘路徑使用佔空比控制電路，並充當電平轉換器。它的最大調整範圍足以抵禦可能的眼睛變形，約為40％至60％。此外，在這項作品中描述了基於傳統CML拓撲的改進的PAM-4組合器，可產生乾淨的56 Gb/s PAM-4訊號。測試晶片在1 V電源電壓下消耗200 mW的功率，並佔用1×0.8 mm$^2$的面積。在差分輸出下，它提供大約600 mV的輸出擺幅，每個電平之間間隔約200 mV。 第二項作品是突發模式應用程序的接收器。該系統可以分別在有效負載和保護時間內在CDR模式和PLL模式之間切換。整個系統可以25.78125 Gb/s或28.05 Gb/s的速度運行，鎖定時間小於100 ns。 CID容限遠遠超過132位。測試晶片在1.2 V和2.5 V電源電壓下的功耗為335 mW，佔用面積為1200 μm x 850 μm。它可以恢復差分輸出的全速率時鐘和數據。

This thesis presents two works. The first work is a prototype transmitter with buit-in PRBS-7 testing pattern and 3-tap FFE. The 3-tap FFE provides maximum boost of approximately 8 dB at 14 GHz. For synthesizing four quarter-rate PRBS sequences with different phases by the multiplexer to half-rate data sequence, a modified 2-to-1 multiplexer is presented. Duty-cycle control circuits are employed along the clock paths and server a role of level converter. Its maximum adjustment range is about 40\% to 60\% enough to counter possible eye distortion. Furthermore, the improved PAM-4 combiner based on traditional CML topology is depicted in this work and results in clean 56 Gb/s PAM-4 signal. The testing chip consumes 200 mW under 1 V supply voltage and occupies 1×0.8 mm$^2$ area. It provides about 600-mV output swing and 200 mV between each level in differential. The second work is a receiver for burst-mode application. This system can be switched between CDR mode and PLL mode during the payload and guard time, respectively. The whole system can be operated at 25.78125 Gb/s or 28.05 Gb/s with the locking time less than 100 ns. The CID tolerance is well beyond than 132 bits. The testing chip consumes 335 mW under 1.2 V and 2.5 V supply voltage and occupies 1200 μm x 850 μm area. It recovers the full-rate clock and data in differential.