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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/21063
完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor陳怡然
dc.contributor.authorShan-En Changen
dc.contributor.author張善恩zh_TW
dc.date.accessioned2021-06-08T03:18:26Z-
dc.date.copyright2017-02-08
dc.date.issued2016
dc.date.submitted2016-12-27
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dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/21063-
dc.description.abstract隨著通訊系統的發展,民間業者不斷地爭取頻段商業化,因此,美國聯邦通訊委員會(FCC)將900 MHz、2.4 GHz以及5.8 GHz三段頻帶,稱為工業科學醫療頻帶(ISM Band)並開放給民間使用。為了能夠同時傳送多頻帶的訊號,傳送端必須具有一個寬頻功率放大器來供使用。
在通訊系統中,常可見到各種調變技術運用於傳送端,而射頻功率放大器在通訊系統中扮演相當重要的角色,是發射機的主要組成部分,其消耗的能量為射頻收發機中的60 ~ 90 %,因此功率放大器消耗程度的效率高低與否,就變得額外重要。
本論文主要分為兩個部分,皆採用0.13微米互補式金屬氧化物半導體(CMOS)製程來製作全積體化的CMOS功率放大器。為了克服CMOS的低崩潰電壓以及提高輸出功率與效率的特性,本論文皆使用堆疊式電晶體(Stacked Transistors)來設計功率放大器。
在論文的第一部分,設計一個應用於ISM band的2 ~ 6 GHz高功率與高效率之寬頻單級功率放大器,架構為堆疊四顆電晶體的功率放大器,並採用網路合成(Network Synthesis)的寬頻匹配方法。此功率放大器,由模擬結果得知,其小訊號增益(S21)的1 dB 頻寬為2 ~ 6 GHz以及3 dB頻寬為 1.6 ~ 6.3 GHz,其1 dB頻寬內,輸出1 dB壓縮功率點(P_1dB)為28.1 ~ 29.1 dBm以及此時的PAE為35.3 ~ 48.66 %,P_sat 為30.9 ~ 31.9 dBm以及此時的PAE為46.6 ~ 50.2 %。其頻寬內包含ISM Band的2.4 GHz(2400 ~ 2500 MHz)及5.8 GHz(5725 ~ 5875 MHz)等兩個頻帶。
在論文的第二部分,脈衝調變功率放大器,架構為一個使用開關鍵控(On-Off Keying, OOK)技術的脈衝調變器及一個雙級高效率功率放大器結合的脈衝調變功率放大器,其中,脈衝調變器由模擬得知,S11與S22小於 – 10 dB的頻寬為590 MHz,S21的3 dB頻寬為500 MHz(1700 ~ 2200 MHz),最低隔離度為65.42 dB;而整體電路在1.9 GHz時,由模擬結果得知,當輸入功率為 – 6 dBm時,其轉換功率增益為34.0 dB,輸出功率為28.0 dBm,此時的PAE為58.9 %。
zh_TW
dc.description.abstractAs the development of communication systems, the industry continues to request more frequency bands. Therefore, the FCC releases 900 MHz, 2.4 GHz and 5.8 GHz bands as the industrial scientific medical band(ISM Band)for openly use. In order to simultaneously transmitting signals in multiple frequency bands, there should be a broadband power amplifier in a transmitter.
In the communication systems, there are variety of modulation techniques. The radio frequency power amplifier is an important component of the transmitter and plays a crucial role in communication systems. It dominates about 60% to 90% of the energy consumptions in the RF transceiver. Therefore, the power-added efficiency, affecting the degree of the power consumption, is distinctly important.
This thesis presents the CMOS power amplifiers that are implemented in 0.13 μm CMOS technology. In order to overcome CMOS transistors’ low breakdown voltage and improve the power and efficiency, this thesis adopts the stacked transistors to design power amplifier.
The first wideband PA is one stage with, high power and high efficiency for ISM band. Circuit architecture uses four-stacked transistors and network synthesis broadband matching. From the simulation, this PA achieves a 1-dB bandwidth of 2 to 6 GHz and 3-dB bandwidth of 1.6 to 6.3 GHz. In the 1-dB bandwidth, this PA achieves P1dB of 28.1 to 29.1 dBm and PAE of 35.27 to 48.66 %;Psat of 30.9 to 31.9 dBm and maximum PAE of 46.61 to 50.15 %. The CMOS PA is able to cover ISM Band 2.4 GHz(2400 ~ 2500 MHz)and 5.8 GHz(5725 ~ 5875 MHz).
The second part of PA is CMOS pulse modulation power amplifier with CMOS pulse modulator, which uses on-off keying technology, and two-stage high efficiency power amplifier. From the simulation, this OOK modulator achieves S11 and S22, less than - 10 dB, with 590 MHz bandwidth. The 3-dB bandwidth of S21 is 500 MHz(1700 ~ 2200 MHz). This pulse modulated power amplifier achieves a power gain of 34.0, output power of 28.0 dBm and PAE of 58.9 % when frequency is 1.9 GHz and input power is – 6 dBm.
en
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en
dc.description.tableofcontents口試委員會審定書 #
中文摘要 i
ABSTRACT iii
目錄 v
圖目錄 ix
表格目錄 xvii
Chapter 1 緒論 1
1.1 研究動機 1
1.2 文獻回顧 2
1.2.1 寬頻功率放大器 2
1.2.2 開關鍵控調變器 14
1.3 論文貢獻 21
1.4 論文架構 21
Chapter 2 堆疊式電晶體之設計 23
2.1 簡介 23
2.2 堆疊式電晶體 23
2.2.1 基本架構 23
2.2.2 閘極電容(Ck) 24
2.2.3 閘極偏壓設定 26
Chapter 3 0.13微米CMOS寬頻功率放大器 29
3.1 簡介 29
3.2 功率放大器設計理論 31
3.3 網路合成寬頻匹配 33
3.3.1 簡介 33
3.3.2 濾波器 33
3.3.3 諾頓轉換 36
3.3.4 結論 42
3.4 寬頻功率放大器研製 43
3.4.1 電路架構 43
3.4.2 寬頻匹配網路 45
3.5 功率放大器模擬結果 53
3.6 量測 61
3.6.1 量測設定 61
3.6.2 量測結果 63
3.7 重新設計電路之模擬結果 66
3.8 結論與討論 69
Chapter 4 0.13微米CMOS脈衝調變功率放大器 77
4.1 簡介 77
4.2 CMOS脈衝調變器研製 78
4.2.1 簡介 78
4.2.2 開關鍵控調變器理論 79
4.2.3 電路架構 82
4.2.4 電路設計 83
4.2.5 模擬結果 98
4.2.6 量測設定 103
4.2.7 結論 105
4.3 CMOS脈衝調變功率放大器研製 108
4.3.1 簡介 108
4.3.2 電路架構 109
4.3.3 電路設計 112
4.3.4 米勒電容 119
4.3.5 模擬結果 127
4.3.6 量測設定 131
4.3.7 結論 133
Chapter 5 結論 135
參考文獻 137
附錄A 143
dc.language.isozh-TW
dc.subject網路合成zh_TW
dc.subject功率放大器zh_TW
dc.subject寬頻zh_TW
dc.subject堆疊式電晶體zh_TW
dc.subject米勒電容zh_TW
dc.subject脈衝調變功率放大器zh_TW
dc.subject高效率zh_TW
dc.subject脈衝調變器zh_TW
dc.subject開關鍵控zh_TW
dc.subjectStacked Transistorsen
dc.subjectPulse Modulator Power Amplifieren
dc.subjectMiller capacitanceen
dc.subjectHigh Efficiencyen
dc.subjectPulse Modulatoren
dc.subjectOn-Off Keyingen
dc.subjectNetwork Synthesisen
dc.subjectPower Amplifieren
dc.subjectWidebanden
dc.titleCMOS寬頻功率放大器及脈衝調變功率放大器zh_TW
dc.titleCMOS Wideband Power Amplifier and Pulse Modulated Power Amplifieren
dc.typeThesis
dc.date.schoolyear105-1
dc.description.degree碩士
dc.contributor.oralexamcommittee邱煥凱,夏勤,劉怡君
dc.subject.keyword堆疊式電晶體,寬頻,功率放大器,網路合成,開關鍵控,脈衝調變器,高效率,米勒電容,脈衝調變功率放大器,zh_TW
dc.subject.keywordStacked Transistors,Wideband,Power Amplifier,Network Synthesis,On-Off Keying,Pulse Modulator,High Efficiency,Miller capacitance,Pulse Modulator Power Amplifier,en
dc.relation.page144
dc.identifier.doi10.6342/NTU201603857
dc.rights.note未授權
dc.date.accepted2016-12-28
dc.contributor.author-college電機資訊學院zh_TW
dc.contributor.author-dept電子工程學研究所zh_TW
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