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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/20638
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dc.contributor.advisor曹恒偉
dc.contributor.authorLi-Ya Huangen
dc.contributor.author黃欐雅zh_TW
dc.date.accessioned2021-06-08T02:56:29Z-
dc.date.copyright2017-08-04
dc.date.issued2017
dc.date.submitted2017-08-03
dc.identifier.citation[1] '科技部專題研究計畫:應用於智慧型標籤之關鍵技術研發,' 2014
[2] 林文一, ” Digital Signal Processing and Architecture Design of Smart Badge Access Point Receiver”, 台大電子所碩士論文,2014
[3] ITU, 'Recommendation ITU-R M.1225 – Guideline for Evaluation of Radio Transmission Technologies for IMT-2000,' 1997.
[4] V. Papamichael, C. Soras and V. Makios, 'FDTD Modeling and Characterization of the Indoor Radio Propagation Channel in the 434 MHz ISM Band,' Applied Electromagnetics and Communications, pp. 217-220, Oct. 2003.
[5]黃議徵, “Low-complexity Solution to GPS Narrowband Interference Cancellation”, 台大電信所碩士論文, 2009
[6] Dixon, Robert C. Spread spectrum systems: with commercial applications. Vol. 994. New York: Wiley, 1994.
[7] 秦茂倫, ” Design of mac protocol for smart badge systems”, 台大電信所碩士論 文,2016
[8] Tomasi, Wayne. Introduction to Data communications and
Networking.Prentice-Hall, Inc., 2004.
[9] Sarwate, Dilip V. 'Computation of cyclic redundancy checks via table look-
up.' Communications of the ACM 31.8 (1988): 1008-1013.
[10] Huo, Yuanhong, et al. 'High performance table-based architecture for parallel CRC calculation.' Local and Metropolitan Area Networks (LANMAN), 2015 IEEE
International Workshop on. IEEE, 2015.
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practical guide. Sams, 2001.
[12] M.P. Fitz, 'Planar Filtered Techniques for Burst Mode Carrier Synchronization,' IEEE GLOBECOM, pp. 365-369, Dec. 1991.
[13] M. Luise and R. Reggiannini, 'Carrier Frequency Recovery in All-Digital Modems for Burst-Mode Transmissions,' IEEE Transactions on Communications, pp.1169-1178, Feb. 1995.
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Transactions on Electronic Computers, pp. 330-334, Sept. 1959.
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[16] K. H. Mueller and M. M¨ uller, “Timing recovery in digital synchronous data
receivers,” IEEE Trans. Commun., vol. 24, pp. 516-531, May 1976.
[17] McLachlan, Geoffrey, and Thriyambakam Krishnan. The EM algorithm and
extensions. Vol. 382. John Wiley & Sons, 2007.
[18] Savazzi, Pietro, and Paolo Gamba. 'Iterative symbol timing recovery for short
burst transmission schemes.' IEEE Transactions on Communications 56.10 (2008).
[19] C. W. Farrow, “A continuously variable digital delay element,” in Proc. IEEE
ISCAS’88, Espoo, Finland, pp, 2641-2645, June 7-9, 1988.
[20] V. Valimaki, 'A new filter implementation strategy for Lagrange
interpolation,' Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on, Seattle, WA, 1995, pp. 361-364 vol.1.
[21] M.-H. Lai, “Clock synchronization of VDSL system,” M.S. thesis, Institute of
Electronics, National Chiao Tung University, Hsin-Chu, Taiwan, May 2004.
[22] Mueller, Kurth, and Markus Muller. 'Timing recovery in digital synchronous data
receivers.' IEEE Transactions on Communications 24.5 (1976): 516-531.
[23] R. Hamila, J. Vesma, M. Renfors, 'Polynomial-based maximum-likelihood technique for synchronization in digital receivers', IEEE Trans. Circuit and Systems II - Analog and Digital Signal Processing, vol. 49, no. 8, pp. 567-576, Aug. 2002.
[24] H. Meyr, M. Moeneclaey, S. A. Fechtel, Digital Communication Receivers, John
Wiley & Sons, 1998.
[25] Mary McCarthy , 'Peak-to-Peak Resolution Versus Effective Resolution,' Analog Device Application Note 615, 2003.
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/20638-
dc.description.abstract本論文自訂應用於短距離無線通訊之智慧型標籤(Smart Badge)系統,使用400MHz生醫通訊傳輸頻帶(Industrial Scientific Medical Band, ISM)進行傳輸,傳輸接收的調變方式為差分正交相移鍵控(Differential Quadrature Phase Shift Keying, DQPSK),因智慧型標籤系統需長時間運作,須具備省電,輕巧的特性,且本系統為多使用者對一基站傳輸系統,各封包會有不同的載波頻率位移及時脈偏移,因此每次接收新的封包需要重新進行同步的估測與補償,且本系統採隨機存取模式通訊協定( random access type),因此封包到達時間未知,所以我們也設計了封包同步的電路。
本研究設計一具低複雜度、低功耗的小型基站接收機,在AWGN通道且最大載波頻率偏移為400MHz的500ppm,最大時脈偏移為傳送時脈的500ppm的環境下,經過降頻428倍將中頻降至基頻後,先進行封包偵測,再依序進行載波頻率、時脈偏移補償、封包確認及循環冗餘校驗等。定點數演算錯誤率在E_b/N_0等於12dB時達到5×〖10〗^(-5),和浮點數計算模擬相差0.3dB。硬體實現使用CIC提供的tsmc 90nm CMOS製程,經APR後晶片操作速度為42.8MHz,核心面積為0.48mm^2,面積利用率為75.6%,功耗為14.2mW。
zh_TW
dc.description.abstractIn this thesis we propose a short-distance wireless communication Smart Badge system, which communicate using the 400MHz ISM bands. Modulation format of the system is DQPSK. Because Smart Badge system should have long standby time, it is designed to save power and have lightweight. And the system is a multiple users system, each packet received at AP may have different Carrier frequency offset and clock offset, so each time we receive a new packet, we need to re-synchronize again. Besides, our system adopts a random access protocol and the its packet arrival time is unknown, so packet synchronization is also necessary.
We design and implement a low complexity, low power Smart Badge base station receiver, which transmitted over AWGN channel, and with a maximum carrier frequency, offset 500 ppm of 400 MHz, and a maximum clock offset is 500 ppm of transmission clock. After down sampled by 428, the IF signal is transmitted to the IF band to baseband, we operate packet detection firstly, and then carrier frequency compensation, clock offset compensation, packet confirmation and cyclic redundancy check. The PER of fixed-point simulation is 5×〖10〗^(-5) at E_b/N_0==12dB, and the difference from floating simulation is 0.3dB. Hardware simulation uses tsmc 90nm CMOS process provided by CIC. The receiver after auto place and routing can operate at 42.8MHz; the core area is 0.48 mm^2 with 68.7% area utilization, and has 11.7mW power consumption.
en
dc.description.provenanceMade available in DSpace on 2021-06-08T02:56:29Z (GMT). No. of bitstreams: 1
ntu-106-R02943018-1.pdf: 6290232 bytes, checksum: 1a78d27f017d88883e8847f20307fbe1 (MD5)
Previous issue date: 2017
en
dc.description.tableofcontents目錄
Abstract……………………….......................................................i
摘要……………………………………………………………....ii
圖索引…………………………………………………………...iii
表索引………………………………………………………...…vi
目錄……………………………………………………………..vii
第一章、緒論 1
1.1 前言 1
1.2 研究動機 2
1.3 論文架構 2
2 第二章、數位接收機規格與簡介 3
2.1 數位接收機規格 3
2.2 DQPSK接收機簡介與設計考量 4
2.2.1 數位降頻 5
2.2.2 載波頻率偏移 6
2.2.3 符元同步與時脈偏移 6
2.2.4 通道考量 6
2.3 自動增益控制 7
2.4 省電考量 8
2.5 使用之封包格式 9
2.5.1 常見前置訊號類型及特性 9
2.5.2 前置訊號選擇 12
3 第三章、循環冗餘校驗 13
3.1 循環冗餘校驗簡介 13
3.2 平行化處理的查表循環冗餘校驗 14
4 第四章、封包偵測及確認 19
4.1 封包偵測性能指標 19
4.2 封包偵測 19
4.3 封包確認 23
5 第五章、接收機載波頻率同步分析與設計 28
5.1 載波頻率偏移偵測頻寬要求 28
5.2 載波頻率偏移粗略偵測與補償 28
5.3 載波頻率偏移精細偵測與補償 29
5.3.1 基頻載波頻率同步演算法 29
5.3.2 座標旋轉數位計算器(CORDIC) 33
5.3.3 載波頻率偏移剩餘相位追蹤 35
6 第六章、接收機符元取樣同步與時脈同步分析與設計 36
6.1 符元取樣同步分析與設計 36
6.2 時脈同步分析與設計 36
6.2.1 時脈同步簡介 36
6.2.2 常見時脈同步演算法 37
6.2.3 Generalized-EM演算法 38
6.2.4 內差濾波器 41
6.2.5 使用Generalized-EM演算法估測之時脈同步演算法 43
7 第七章、系統模擬與硬體實現 48
7.1 模擬環境 48
7.2 定點數分析與模擬 48
7.3 硬體合成與電路模擬 53
7.4 晶片實現結果 54
8 第八章、結論與未來展望 56
8.1 結論 56
8.2 未來展望 57
9 參考資料 58
dc.language.isozh-TW
dc.title應用於智慧型標籤基站接收機之低複雜度DQPSK封包接收機設計zh_TW
dc.titleLow Complexity DQPSK Packet Receiver Design for Smart Badge Access Point Receiveren
dc.typeThesis
dc.date.schoolyear105-2
dc.description.degree碩士
dc.contributor.oralexamcommittee蔡佩芸,黃崇禧,陳家偉
dc.subject.keyword數位訊號處理,封包偵測,低複雜度,架構設計,封包接收機,zh_TW
dc.subject.keyworddigital signal processing,packet detection,low complexity,architecture design,burst receiver,en
dc.relation.page60
dc.identifier.doi10.6342/NTU201702120
dc.rights.note未授權
dc.date.accepted2017-08-03
dc.contributor.author-college電機資訊學院zh_TW
dc.contributor.author-dept電子工程學研究所zh_TW
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