25-Gb/s 光通訊接收器設計

Yang-Yang Fu; 付陽陽

請用此 Handle URI 來引用此文件： http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/20295

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.advisor	李致毅(Jri Lee)
dc.contributor.author	Yang-Yang Fu	en
dc.contributor.author	付陽陽	zh_TW
dc.date.accessioned	2021-06-08T02:44:24Z	-
dc.date.copyright	2018-01-27
dc.date.issued	2018
dc.date.submitted	2018-01-11
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dc.identifier.uri	http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/20295	-
dc.description.abstract	隨著通訊系統對資料傳送速率的要求越來越高，100-Gb/s 乙太網路系統將開始全面普及。作為乙太網路系統的重要組成部分，光通訊接收器電路的設計顯得尤為關鍵。本論文第一部分介紹了100-Gb/s 乙太網路系統，以及提出了一個突發模式接收器前端電路，可以在幾百納秒以內完成漂移校正。本論文第二部分提出了一個使用40 納米互補式金屬氧化半導體制程製作之應用於100-Gb/s 乙太網路的25∼28-Gb/s 光通訊接收器，此接收器包括一個RGC 跨阻放大器，若干限幅放大器，連續時間線性等化器，時鐘資料恢復電路以及前饋等化器。此接收器還有一個10-Gb/s 的工作模式，此模式下關閉時鐘資料恢復電路和前饋等化器。RGC 跨阻放大器因為有著更小的輸入電阻，所以在輸入寄生電容一樣的情況下有著更好的頻寬。兩級連續時間線性等化器也可以提供9 dB 的均衡。為了抵消輸出的綁線電感和背板走線的頻寬損失，採用前饋等化器作輸出。在電域測試中，10-Gb/s 資料在關閉時鐘資料恢復電路模式下靈敏度為1.9mVpp，25-Gb/s 速率下靈敏度為17.6 mVpp，並且誤碼率均小於〖10〗^(-12)，接收器的輸入參考雜訊為2.73 uArms。前饋等化器輸出擺幅為375∼931 mVppd，最大均衡能力為8.5 dB。時鐘資料恢復電路在25-Gb/s 速率下的帶外抖動容忍為0.134 UI，在28-Gb/s 速率下抖動容忍為0.148 UI，鎖定時間在微秒等級。	zh_TW
dc.description.abstract	The data transmission speed is getting faster and faster in communication system nowadays, 100-Gb/s Ethernet system will be popular. As an important part of the Ethernet system, the design of the optical communication receiver integrated circuits is particularly critical. The first part of this thesis provides a brief description of 100-Gb/s Ethernet system and proposes a burst mode front-end circuit, which can finish DC-offset calibration in hundreds of nanoseconds. The second part of this thesis presents a 25∼28-Gb/s optical communication receiver for 100-Gb/s Ethernet fabricated in 40nm CMOS. This receiver includes a RGC TIA, several limiting amplifiers (LAs) and two continuous time linear equalizers (CTLEs), a clock and data recovery circuit (CDR), and a feedforward equalizer (FFE). The receiver also has a 10-Gb/s operation mode, we will bypass CDR and FFE in this mode. RGC TIA has a smaller input resistance, so it has better bandwidth with the same input parasitic capacitance compared with other kinds of TIA. Two-stage CTLEs can provide 0∼9 dB boosting. 3-tap FFE is applied to overcome the channel loss caused by bonding wire and PCB trace. Testing under electric domain, the sensitivity is 1.9 mVpp for 10-Gb/s mode, and 17.6 mVpp for 25-Gb/s mode, where the bit error rate is less than 〖10〗^(-12), respectively. FFE output swing varies from 375∼931 mVppd, maximum boosting is 8.5 dB. The out-band jitter tolerance is 0.134 UI for 25-Gb/s and 0.148 UI for 28-Gb/s. CDR locking time is in microseconds.	en
dc.description.provenance	Made available in DSpace on 2021-06-08T02:44:24Z (GMT). No. of bitstreams: 1 ntu-107-R04943157-1.pdf: 13341592 bytes, checksum: e4d6ae69012a57df082259e9d4d4278f (MD5) Previous issue date: 2018	en
dc.description.tableofcontents	Contents 中文摘要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 A 25-Gb/s Burst Mode Front-end Circuit . . . . . . . . . . . . . . . . . . . . 3 2.1 Introduction of 100GbE System . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 Architecture and Building Blocks . . . . . . . . . . . . . . . . . . . . . . 4 2.2.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2.2 Limiting Amplifiers and Equalizers . . . . . . . . . . . . . . . . . . 5 2.2.3 Calibration Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3.1 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 A 25-Gb/s Continuous Mode Optical Receiver . . . . . . . . . . . . . . . . . 13 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Architecture and Building Blocks . . . . . . . . . . . . . . . . . . . . . . 14 vii doi:10.6342/NTU201800046 3.2.1 Front-end Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.1.1 Transimpedance Amplifiers . . . . . . . . . . . . . . . . . 15 3.2.1.2 Limiting Amplifiers . . . . . . . . . . . . . . . . . . . . . 23 3.2.1.3 Continious Time Linear Equalizers . . . . . . . . . . . . . 28 3.2.2 Feedforward Equalizer . . . . . . . . . . . . . . . . . . . . . . . . 32 3.2.3 Clock and Data Recovery circuit . . . . . . . . . . . . . . . . . . . 36 3.2.3.1 Phase Detector and Delay Calibration Circuits . . . . . . . 37 3.2.3.2 Frequency Detector and Lock Detector . . . . . . . . . . . 40 3.2.3.3 VCO, Clock Buffer and Loop Filter . . . . . . . . . . . . . 42 3.3 Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.1 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . 47 4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
dc.language.iso	zh-TW
dc.title	25-Gb/s 光通訊接收器設計	zh_TW
dc.title	25-Gb/s Optical Communication Receiver Design	en
dc.type	Thesis
dc.date.schoolyear	106-1
dc.description.degree	碩士
dc.contributor.oralexamcommittee	劉宗德(Tsung-Te Liu),彭朋瑞(Peng-Jui Peng)
dc.subject.keyword	跨阻放大器，限幅放大器，連續時間線性等化器，時脈資料恢復，前饋均衡，抖動容忍，靈敏度,	zh_TW
dc.subject.keyword	transimpedance amplifier,limiting amplifier,continuous time linear equalizer,feedforward equalizer,jitter tolerance,sensitivity,	en
dc.relation.page	56
dc.identifier.doi	10.6342/NTU201800046
dc.rights.note	未授權
dc.date.accepted	2018-01-12
dc.contributor.author-college	電機資訊學院	zh_TW
dc.contributor.author-dept	電子工程學研究所	zh_TW
顯示於系所單位：	電子工程學研究所

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