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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 呂學士(Shey-Shi Lu) | |
| dc.contributor.author | Wei-Chen Li | en |
| dc.contributor.author | 李葦宸 | zh_TW |
| dc.date.accessioned | 2021-06-08T02:22:59Z | - |
| dc.date.copyright | 2015-09-17 | |
| dc.date.issued | 2015 | |
| dc.date.submitted | 2015-08-19 | |
| dc.identifier.citation | [1] B. Razavi, Principles of Data Conversion System Design, IEEE Press, 1995.
[2] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001. [3] T. C. Carusone, D. Johns, and K. Martin, Analog Integrated Circuit Desgin, John Wiley & Sons, Inc., 2012. [4] P. H. Fang, Design and Application of Low Power Pipelined and SAR Analog-to-Digital Converters, National Taiwan University MS Thesis, 2009. [5] H. W. Chang, A Low Power Analog-to-Digital Converter for ECG Signal Monitoring System Application, National Taiwan University MS Thesis, 2012. [6] F. Kuttner, 'A 1.2V 10b 20MSample/s Non-Binary Successive Approximation ADC in 0.13um CMOS,' in IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, CA, USA, 2002. [7] S. W. M. Chen and R. W. Brodersen, 'A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-um CMOS,' IEEE Journal of Solid-State Circuits, pp. 2669-2680, Dec. 2006. [8] H. Y. Yang and R. Sarpeshkar, 'A Bio-Inspired Ultra-Energy-Efficient Analog-to-Digital Converter for Biomedical Applications,' IEEE Transactions on Circuits and System I, pp. 2349-2356, Nov. 2006. [9] H. C. Hong and G. M. Lee, 'A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC,' IEEE Journal of Solid-State Circuits, pp. 2161-2168, Oct. 2007. [10] B. P. Ginsburg and A. P. Chandrakasan, 'Highly Interleaved 5-bit, 250-MSample/s, 1.2-mW ADC With Redundant Channels in 65-nm CMOS,' IEEE Journal of Solid-State Circuits, pp. 2641-2650, Dec. 2008. [11] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, 'A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13 um CMOS process,' in Symposium on VLSI Circuits, Kyoto, Japan, 2009. [12] C. C. Liu, S. J. Chang, G. Y. Huang, Y. Z. Lin, C. M. Huang, C. H. Huang, L. Bu, and C. C. Tasi, 'A 10b 100MS/s 1.13mW SAR ADC with Binary-Scaled Error Compensation,' in IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, CA, 2010. [13] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, 'A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procudure,' IEEE Journal of Solid-State Circuits, pp. 731-740, Apr. 2010. [14] V. Hariprasath, J. Guerber, S. H. Lee,and U. K. Moon, 'Merged capacitor switching based SAR ADC with highest switching energy-efficiency,' Electronics Letters, pp. 620-621, Apr. 2010. [15] T. C. Lu, L. D. Van, C. S. Lin, and C. M. Huang, 'A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/conversion-step SAR ADC for Biomedical Applications,' in IEEE Custom Integrated Circuits Conference, San Jose, CA, 2011. [16] S. H. Cho, C. K. Lee, J. K. Kwon, and S. T. Ryu, 'A 550-uW 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction,' IEEE Journal of Solid-State Circuits, pp. 1881-1892, Aug. 2011. [17] S. O'Driscoll, K. V. Shenoy, and T. H. Meng, 'Adaptive Resolution ADC Array for an Implantable Neural Sensor,' IEEE Transactions on Biomedical Circuits and Systems, pp. 120-130, Apr. 2011. [18] G. Y. Huang, S. J. Chang, C. C. Liu, and Y. Z. Lin, 'A 1-uW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications,' IEEE Journal of Solid-State Circuits, pp. 2783-2795, Nov. 2012. [19] J. Y. Lin and C. C. Hsieh, 'A 0.3 V 10-bit 1.12 f SAR ADC With Merge and Split Switching in 90 nm CMOS,' IEEE Transactions on Circuits and Systems I, pp. 70-79, Jan. 2015. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19850 | - |
| dc.description.abstract | 在世界各地的大多數已開發國家，人口老齡化是一個普遍觀察到的現象。而電機電子領域人將研究重點從消費性電子產品轉向生醫應用。在這個趨勢下，我們設計適合應用於生醫系統的類比數位轉換器。
在本論文的第二章，我們將先介紹類比數位轉換器的基本理論。 在本論文的第三章，我們介紹一種利用單調式切換電容以減少功耗的連續漸進式類比數位轉換器。 在本論文的第四章，我們介紹一個輔助牙醫師診斷、治療阻塞性睡眠呼吸中止症的生醫系統晶片。 這些晶片都是使用UMC 0.18um CMOS的製程實現。 | zh_TW |
| dc.description.abstract | Ageing population is a commonly observed phenomenon in most developed countries all over the world. Electrical engineers have turned their attention from consumer products to application in biomedical. We design ADCs that are suitable for biomedical application under this trend.
In chapter 2, the fundamentals of analog-to-digital converters is introduced. In chapter 3 of this thesis, a low power successive approximation register analog-to-digital converter (SAR ADC) using monotonic switching procedure to decrease the power consumption is presented. In chapter 4 of this thesis, a biomedical system on chip (SoC) for smart oral appliance is introduced. These chips are fabricated in UMC 0.18 um CMOS process and the measurement results will be shown. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T02:22:59Z (GMT). No. of bitstreams: 1 ntu-104-R02943078-1.pdf: 4886412 bytes, checksum: fc1a53520b7a651f26e3210167bb9600 (MD5) Previous issue date: 2015 | en |
| dc.description.tableofcontents | 誌謝 i
中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vii LIST OF TABLES x Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 The Fundamentals of Analog-to-Digital Converters 3 2.1 Introduction 3 2.2 Performance evaluation parameters 4 2.2.1 Resolution 4 2.2.2 Offset Error and Gain Error 4 2.2.3 Differential Nonlinearity （DNL） 5 2.2.4 Integral Nonlinearity（INL） 6 2.2.5 Signal-to-Noise Ratio（SNR） 7 2.2.6 Signal-to-Noise and Distortion Ratio（SNDR） 7 2.2.7 Effective Number of Bits（ENOB） 7 2.2.8 Total Harmonic Distortion（THD） 8 2.2.9 Spurious Free Dynamic Range（SFDR） 8 2.2.10 Dynamic Range 9 2.3 ADC Architectures 10 2.3.1 Flash ADC 10 2.3.2 Successive Approximation ADC 11 2.3.3 Pipelined ADC 13 2.3.4 Delta-Sigma ADC 13 Chapter 3 A 1V, 10-bit, Low Power Successive Approximation ADC 16 3.1 Introduction 16 3.2 SAR ADC Architecture 17 3.2.1 Basic Operation Principle of the SAR ADC 17 3.2.2 Circuit Implementation 22 3.3 Building Blocks Implementation 25 3.3.1 Sample and Hold Circuit 25 3.3.2 Dynamic Comparator 31 3.3.3 SAR Control Logic 34 3.3.4 Capacitor Array 36 3.4 Simulation Results 38 3.4.1 Function Simulation 38 3.4.2 Static Performance Simulation 39 3.4.3 Dynamic Performance Simulation 42 3.5 Measurement Results 45 3.5.1 The PCB Design 49 3.5.2 Measurement Setup 50 3.5.3 Static Performance Measurement 51 3.5.4 Dynamic Performance Measurement 53 3.5.5 Performance Metric 56 Chapter 4 A Biomedical SoC for Smart Oral Appliance 57 4.1 Introduction 57 4.2 SoC Architecture 60 4.3 Building Blocks 61 4.3.1 Wireless Charging and Power Management 61 4.3.2 Analog Front End 65 4.3.3 Analog-to-Digital Converter 71 4.3.4 Digital Circuit 76 4.3.5 Transceiver 77 4.4 Chip Layout 81 Chapter 5 Conclusion 83 References 84 | |
| dc.language.iso | en | |
| dc.title | 應用於生醫系統之類比數位轉換器 | zh_TW |
| dc.title | Analog-to-Digital Converter for Biomedical System | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 103-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 孫台平,楊燿州,彭盛裕,游世安 | |
| dc.subject.keyword | 連續漸進式類比數位轉換器,低功耗,生醫系統晶片, | zh_TW |
| dc.subject.keyword | Successive approximation analog-to-digital converter,low power,biomedical system on chip, | en |
| dc.relation.page | 86 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2015-08-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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