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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 楊宏智 | |
dc.contributor.author | Chia-Shiun Tsai | en |
dc.contributor.author | 蔡佳勳 | zh_TW |
dc.date.accessioned | 2021-06-08T02:22:18Z | - |
dc.date.copyright | 2015-08-28 | |
dc.date.issued | 2015 | |
dc.date.submitted | 2015-08-19 | |
dc.identifier.citation | 參考文獻 [1] J. H. Lau, 'Overview and outlook of through-silicon via (TSV) and 3D integrations,' Microelectronics International, vol. 28, pp. 8-22, 2011. [2] Y. Development. (2012). 3DIC TSV interconnects. [3] A. Lab. (2012, July 12). Architecture, Reliability, and Testing Innovation Framework for 3D ICs. [4] K. H. Lu, S.-K. Ryu, Q. Zhao, X. Zhang, J. Im, R. Huang, et al., 'Thermal stress induced delamination of through silicon vias in 3-D interconnects,' in Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th, 2010, pp. 40-45. [5] S.-C. Tseng, 'Manufacturing analysis and application of through silicon via (TSV) wafer,' Master, Department of Mechanical Engineering, National Taiwan University, 2012. [6] D. Z. Pan, S. K. Lim, K. Athikulwongse, M. Jung, J. Mitra, J. Pak, et al., 'Design for manufacturability and reliability for TSV-based 3D ICs,' in Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific, 2012, pp. 750-755. [7] Y. Sun, S. E. Thompson, and T. Nishida, Strain effect in semiconductors: theory and device applications: Springer Science Business Media, 2009. [8] S.-K. Ryu, K.-H. Lu, T. Jiang, J.-H. Im, R. Huang, and P. S. Ho, 'Effect of thermal stresses on carrier mobility and keep-out zone around through-silicon vias for 3-D integration,' Device and Materials Reliability, IEEE Transactions on, vol. 12, pp. 255-262, 2012. [9] J.-S. Yang, K. Athikulwongse, Y.-J. Lee, S. K. Lim, and D. Z. Pan, 'TSV stress aware timing analysis with applications to 3D-IC layout optimization,' in Proceedings of the 47th Design Automation Conference, 2010, pp. 803-806. [10] K. H. Lu, X. Zhang, S.-K. Ryu, J. Im, R. Huang, and P. S. Ho, 'Thermo-mechanical reliability of 3-D ICs containing through silicon vias,' in Electronic Components and Technology Conference, 2009. ECTC 2009. 59th, 2009, pp. 630-634. [11] C. S. Selvanayagam, J. H. Lau, X. Zhang, S. Seah, K. Vaidyanathan, and T. Chai, 'Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps,' Advanced Packaging, IEEE Transactions on, vol. 32, pp. 720-728, 2009. [12] S.-K. Ryu, K.-H. Lu, X. Zhang, J.-H. Im, P. S. Ho, and R. Huang, 'Impact of near-surface thermal stresses on interfacial reliability of through-silicon vias for 3-D interconnects,' Device and Materials Reliability, IEEE Transactions on, vol. 11, pp. 35-43, 2011. [13] M. Liao, 'The reduction of keep-out zone (∼ 10×) by the optimized novel trench structures near the through silicon vias for the application in 3-dimensional integrated circuits,' Journal of Applied Physics, vol. 114, p. 153515, 2013. [14] 林麗娟, 'X光繞射原理極其應用,' 工業材料, vol. 86, p. 101, 1994. [15] 黃宏勝、李麗娟, 'FE-SEM/CL/EBSD分析技術,' 工業材料雜誌2003. [16] 趙振良, '運用顯微拉曼光譜技術分析單晶矽奈米結構之應力分佈,' 碩士, 電子工程研究所, 國立清華大學, 新竹市, 2012. [17] 黃柏益, '利用顯微拉曼光譜分析三維矽通孔表面結構應力分佈,' 碩士, 奈米科學研究所, 中興大學, 台中市, 2013. [18] I. De Wolf, H. Maes, and S. K. Jones, 'Stress measurements in silicon devices through Raman spectroscopy: bridging the gap between theory and experiment,' Journal of Applied Physics, vol. 79, pp. 7148-7156, 1996. [19] E. Anastassakis, A. Pinczuk, E. Burstein, F. H. Pollak, and M. Cardona, 'Effect of static uniaxial stress on the Raman spectrum of silicon,' Solid State Communications, vol. 8, pp. 133-138, 1/15/ 1970. [20] X. Pan, C. W. Tan, J. Miao, J. Kasim, Z. Shen, and E. Xie, 'The stress analysis of Si MEMS devices by micro-Raman technique,' Thin Solid Films, vol. 517, pp. 4905-4908, 2009. [21] X. Wu, J. Yu, T. Ren, and L. Liu, 'Micro-Raman spectroscopy measurement of stress in silicon,' Microelectronics journal, vol. 38, pp. 87-90, 2007. [22] E. Beyne, 'High-bandwidth Chip-to-chip Interfaces : 3D Stacking, Interposer and Optical I/O,' IMEC2013. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19839 | - |
dc.description.abstract | 隨著科技的發展,電子產品往輕、薄、短、小的方向發展,然而線寬越小,越逼近物理極限,製程成本也越高,因此有More-than-Moore的概念提出,透過2.5D-IC與3D-IC的構造與技術,讓不同元件可以垂直方向堆疊達到異質整合,縮小體積並提升傳輸速度,其中矽導穿孔在垂直方向訊號傳輸扮演一個重要的角色。 目前金屬銅為矽導穿孔廣泛使用填充的金屬之一,但銅與矽晶圓兩者材料的熱膨脹係數相差約六倍之多,因此當填完銅的矽導穿孔晶圓經過高溫的製程時,會因為溫度變化使得銅與矽的膨脹或收縮量不一樣,導致在接觸面周圍產生熱應力,影響元件特性與可靠度。本論文透過拉曼光譜量測應力與有限元素分析法模擬出不同孔徑大小的矽導穿孔在高溫時產生之熱應力,並藉由矽導通孔在出口端圓導角的最佳化設計,有效降低矽導通孔在尖角處應力集中效應,同時,也可以減少熱應力影響區域,增加元件可放置區域面積,提升效益。 | zh_TW |
dc.description.abstract | With the development of technology, the electronic products become lighter, smaller and thinner. However, IC manufacturing faces the challenges of physical limits and the cost of processes become higher. Consequently, the conception of More-than-Moore is presented and also allows the Moore’s law to continue. We are able to stack the chips vertically to provide heterogeneous integration, increase the speed and reduce form factor by 3D IC and 2.5D TSV interconnect. The structure of TSV plays an important role in signal transmission between different chips. Nowadays, copper is widely used for the metal filling material in TSV structure. Nevertheless, the coefficient of thermal expansion (CTE) of copper and silicon are quite different. The CTE of copper is about six times higher than silicon. While the temperature changing, the local thermal expansion mismatch would happen. As a result, it will create large thermal stresses and strains at the interface between silicon and copper. The thermal stress may causes the reliability issue and carrier mobility variation. The finite element analysis (FEA) ANSYS software is used for the all the simulations in this paper. The simulation results would compare with the data measured by Raman spectroscopy to verify the models. Round corner TSV design is added to TSV structure to reduce the thermal stress at the interface. With this design, the area of Keep-out-zone could also become smaller and enhance the performance. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T02:22:18Z (GMT). No. of bitstreams: 1 ntu-104-R02522718-1.pdf: 8307265 bytes, checksum: 429cdb2ccb78b76a33b0a906230f3f4c (MD5) Previous issue date: 2015 | en |
dc.description.tableofcontents | 口試委員會審定書 II 致謝 III 摘要 IV Abstract V 目錄 VI 圖目錄 X 表目錄 XV 第一章 緒論 1 1.1 研究背景 1 1.2 研究動機 3 1.3 研究目的 5 1.4 研究架構 7 1.5 論文架構 9 第二章 文獻回顧 11 2.1 簡介 11 2.2 應變矽 12 2.3 Keep-out-zone 15 2.4 不同尺寸的矽導穿孔對熱應力之影響 17 2.5 不同降低熱應力之方法 20 2.5.1 填充緩衝物質之矽導穿孔結構 21 2.5.2 環狀金屬填充之矽導穿孔結構 22 2.5.3 以溝槽設計減緩熱應力之傳遞 24 2.6 小結 27 第三章 實驗規劃與分析方法 28 3.1 簡介 28 3.2 應力量測 28 3.2.1 X光繞射分析法 29 3.2.2 背向式散射繞射電子束 30 3.2.3 拉曼光譜分析法 31 3.3 拉曼量測試片製備 33 3.4 拉曼光譜分析儀 38 3.4.1 拉曼光譜量測機台介紹 38 3.4.2 拉曼光譜量測前校正 42 3.5 拉曼量測結果與應力關係式 45 3.5.1 攝氏200度殘留應力 46 第四章 實驗結果分析與探討 48 4.1 簡介 48 4.2 參數設定 50 4.2.1 材料參數設定 50 4.2.2 邊界條件設定 50 4.3 殘留應力模擬分析 52 4.3.1 攝氏200度退火之殘留應力模擬 52 4.4 DRIE鑽孔熱應力之模擬分析 54 4.4.1 2μm×30μm TSV 55 4.4.1.1 無圓導角設計 55 4.4.1.2 半徑0.1μm圓導角設計 55 4.4.1.3 半徑0.5μm圓導角設計 56 4.4.1.4 半徑1μm圓導角設計 56 4.4.1.5 各規格比較 57 4.4.2 5μm×50μm TSV 58 4.4.2.1 無圓導角設計 58 4.4.2.2 半徑0.3μm圓導角設計 58 4.4.2.3 半徑0.5μm圓導角設計 59 4.4.2.4 半徑1μm圓導角設計 59 4.4.2.5 各規格比較 60 4.4.3 10μm×100μm TSV 61 4.4.3.1 無圓導角設計 61 4.4.3.2 半徑0.3μm圓導角設計 錯誤! 尚未定義書籤。 4.4.3.3 半徑0.5μm圓導角設計 61 4.4.3.4 半徑2μm圓導角設計 62 4.4.3.5 半徑3μm圓導角設計 62 4.4.3.6 各規格比較 63 4.4.4 50μm×300μm TSV 64 4.4.4.1 無圓導角設計 64 4.4.4.2 半徑1μm圓導角設計 64 4.4.4.3 半徑5μm圓導角設計 65 4.4.4.4 半徑10μm圓導角設計 65 4.4.4.5 各規格比較 66 4.4.5 100μm×300μm TSV 67 4.4.5.1 無圓導角設計 67 4.4.5.2 半徑4μm圓導角設計 67 4.4.5.3 半徑6μm圓導角設計 68 4.4.5.4 半徑10μm圓導角設計 68 4.4.5.5 半徑15μm圓導角設計 69 4.4.5.6 各規格比較 70 小結 71 第五章 結果討論與未來展望 72 5.1 結論 72 5.2 未來展望 73 參考文獻 74 | |
dc.language.iso | zh-TW | |
dc.title | 圓導角設計對矽導穿孔結構之熱應力分析與模擬 | zh_TW |
dc.title | The Analysis and Simulation of the Thermal Stress Induced by Through-Silicon Via (TSV) with Round Corner Structure | en |
dc.type | Thesis | |
dc.date.schoolyear | 103-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 陳炤彰,李貫銘,黃吉宏,廖學專 | |
dc.subject.keyword | 矽導通孔,熱應力,圓導角,有限元素法, | zh_TW |
dc.subject.keyword | Through-silicon via (TSV),Round corner,Thermal stress,Finite element analysis (FEA), | en |
dc.relation.page | 76 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2015-08-19 | |
dc.contributor.author-college | 工學院 | zh_TW |
dc.contributor.author-dept | 機械工程學研究所 | zh_TW |
顯示於系所單位: | 機械工程學系 |
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