請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19731
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
dc.contributor.author | Chun-Chang Yu | en |
dc.contributor.author | 余俊璋 | zh_TW |
dc.date.accessioned | 2021-06-08T02:15:54Z | - |
dc.date.copyright | 2021-02-20 | |
dc.date.issued | 2021 | |
dc.date.submitted | 2021-02-06 | |
dc.identifier.citation | [1] W. Tang, A. Veidenbaum, A. Nicolau, and R. Gupta, “Integrated i-cache way predictor and branch target buffer to reduce energy consumption,” in International Symposium on High Performance Computing, pp. 120–132, Springer, 2002. [2] M. D. Powell, A. Agarwal, T. Vijaykumar, B. Falsafi, and K. Roy, “Reducing set-associative cache energy via way-prediction and selective direct-mapping,” in Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, pp. 54–65, IEEE Computer Society, 2001. [3] K. Inoue, T. Ishihara, and K. Murakami, “Way-predicting set-associative cache for high performance and low energy consumption,” in Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No. 99TH8477), pp. 273–275, IEEE, 1999. [4] C.-L. Yang and C.-H. Lee, “Hotspot cache: joint temporal and spatial locality exploitation for i-cache energy reduction,” in Proceedings of the 2004 international symposium on Low power electronics and design, pp. 114–119, ACM, 2004. [5] A. Sembrant, E. Hagersten, and D. Black-Shaffer, “Tlc: A tag-less cache for reducing dynamic first level cache energy,” in 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 49–61, IEEE, 2013. [6] W. Zhang, H. Zhang, and J. Lach, “Reducing dynamic energy of set-associative l1 instruction cache by early tag lookup,” in 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 49–54, IEEE, 2015. [7] K. Asanovi´c and D. A. Patterson, “Instruction sets should be free: The case for risc-v,” EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2014-146, 2014. [8] N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, and et al., “The gem5 simulator,” SIGARCH Comput. Archit. News, vol. 39, p. 1–7, Aug. 2011. [9] G. Reinman, B. Calder, and T. Austin, “Optimizations enabled by a decoupled front-end architecture,” IEEE Transactions on Computers, vol. 50, no. 4, pp. 338–355, 2001. [10] J. L. Henning, “Spec cpu2006 benchmark descriptions,” SIGARCH Comput. Archit. News, vol. 34, p. 1–17, Sept. 2006. [11] S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi, “Mcpat: An integrated power, area, and timing modeling framework for multicore and manycore architectures,” in 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 469–480, Dec 2009. [12] A. Bardizbanyan, M. Sj¨alander, D. Whalley, and P. Larsson-Edefors, “Speculative tag access for reduced energy dissipation in set-associative l1 data caches,” in IEEE 31st International Conference on Computer Design (ICCD), pp. 302–308, 2013. [13] A. Bardizbanyan, M. Sj¨alander, D. Whalley, and P. Larsson-Edefors, “Reducing set-associative l1 data cache energy by early load data dependence detection (eld3),” in 2014 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1–4, March 2014. [14] J. Dai, M. Guan, and L. Wang, “Exploiting early tag access for reducing l1 data cache energy in embedded processors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, pp. 396–407, Feb 2014. [15] Burn J. Lin, 'Future of multiple-e-beam direct-write systems,' Journal of Micro/Nanolithography, MEMS, and MOEMS, vol. 11, no. 3, p. 033011, Sep 2012. [16] Burn J. Lin, Optical Lithography: Here is Why, 1st ed, pp. 95–132 and 323–441, SPIE, Washington, United States, 2009. [17] S. J. Lin, W. C. Wang, P. S. Chen, C. Y. Liu, T. N. Lo, Jack J. H. Chen, Faruk Krecinic, Burn J. Lin, 'Characteristics performance of production-worthy multiple e-beam maskless lithography,' Proc. SPIE, vol. 7637, Alternative Lithographic Technologies II, p. 763717, Apr 2010. [18] Shy-Jay Lin, Pei-Yi Liu, Cheng-Hung Chen, Wen-Chuan Wang, Jaw-Jung Shin , Burn Jeng Lin, Mark A. McCord, Sameet K. Shriyan, 'Influence of data volume and EPC on process window in massively parallel e-beam direct write,' Proc. SPIE, vol. 8680, Alternative Lithographic Technologies V, p. 86801C, Mar 2013. [19] E. Slot et al., “MAPPER: high throughput maskless lithography,” Proc. SPIE, vol. 6921, p. 69211P, 2008. [20] G. de Boer et al., “MAPPER: progress towards a high volume manufacturing system,” Proc. SPIE, vol. 8680, p. 86800O, 2013. [21] J. Belledent et al., “Matching of beams on the MAPPER MATRIX tool: a simulation study,” Proc. SPIE, vol. 8680, p. 86800J, 2013. [22] P. Petric et al., “REBL nanowriter: reflective electron beam lithography,” Proc. SPIE, vol. 7271, p. 727107, 2009. [23] A. Carroll et al., “The REBL DPG: recent innovations and remaining challenges,” Proc. SPIE, vol. 9049, p. 904917, 2014. [24] E. Platzgummer, “Maskless lithography and nanopatterning with electron and ion multibeam projection,” Proc. SPIE, vol. 7637, p. 763703, 2010. [25] E. Platzgummer, C. Klein, and H. Loeschner, “eMET POC: realization of a proof-of-concept 50 keV electron multibeam mask exposure tool,” Proc. SPIE, vol. 8166, p. 816622, 2011. [26] E. Platzgummer, C. Klein, and H. Loeschner, “Electron multibeam technology for mask and wafer writing at 0.1 nm address grid,” Journal of Micro/Nanolithography, MEMS, and MOEMS, vol. 12, no. 3, p. 031108, 2013. [27] T. Gubiotti et al., “Reflective electron beam lithography: lithography results using CMOS controlled digital pattern generator chip,” Proc. SPIE, vol. 8680, p. 86800H, 2013. [28] Chin-Khai Tang, Ming-Shing Su, Yi-Chang Lu, 'Efficient layout data compression algorithm and its low-complexity, high-performance hardware decoder implementation for multiple electron-beam direct-write systems,' Journal of Micro/Nanolithography, MEMS, and MOEMS, vol. 14, no. 3, p. 031212, Aug 2015. [29] P. C. Lin, Y. H. Pai, Y. H. Chiu, S. Y. Fang and C. C. P. Chen, 'Lossless compression algorithm based on dictionary coding for multiple e-beam direct write system,' in 2016 Design, Automation Test in Europe Conference Exhibition (DATE), Dresden, pp. 285-288, 2016. [30] Cheng-Chi Wu, Jensen Yang, Wen-Chuan Wang, Shy-Jay Lin, “An Instruction-based High-Throughput Lossless Decompression Algorithm for E-Beam Direct-Write System,” Proc. SPIE, vol. 9423, Alternative Lithographic Technologies VII, p. 94231P, 2015. [31] V. Dai and A. Zakhor, “Lossless compression of VLSI layout image data,” IEEE transactions on image processing, vol. 15, no. 9, pp. 2522–2530, 2006. [32] H. Liu, V. Dai, A. Zakhor, and B. Nikolic, “Reduced complexity compression algorithms for direct-write maskless lithography systems,” Journal of Micro/Nanolithography, MEMS, and MOEMS, vol. 6, no. 1, p. 013007, 2007. [33] V. Dai, “Data compression for maskless lithography systems: architecture, algorithms and implementation,” Ph.D. Dissertation, Department of Electrical Engineering and Computer Sciences, Univ. of California at Berkeley, California, United States, 2008. [34] G. Cramer, H.-I. Liu, and A. Zakhor, “Lossless compression algorithm for REBL direct-write e-beam lithography system,” Proc. SPIE, vol. 7637, p. 76371L, 2010. [35] J. Yang and S. A. Savari, “A lossless circuit layout image compression algorithm for maskless lithography systems,” in Proc. of the 2010 Data Compression Conf., pp. 109–118, IEEE, Snowbird, UT, 2010. [36] J. Yang and S. A. Savari, “Transform-based lossless image compression algorithm for electron beam direct write lithography systems,” in Recent Advances in Nanofabrication Techniques and Applications, B. Cui, Ed., pp. 95–110, InTech, Rijeka, Croatia, 2011. [37] J. Yang and S. A. Savari, “Lossless circuit layout image compression algorithm for maskless direct write lithography systems,” Journal of Micro/Nanolithography, MEMS, and MOEMS, vol. 10, no. 4, p. 043007, 2011. [38] J. Yang and S. A. Savari, “Improvements on Corner2, a lossless layout image compression algorithm for maskless lithography systems,” Proc. SPIE, vol. 8352, p. 83520K, 2012. [39] J. Yang, X. Li, and S. A. Savari, “Hardware implementation of Corner2 lossless compression algorithm for maskless lithography systems,” Proc. SPIE, vol. 8323, p. 83232O, 2012. [40] J. Yang, S. A. Savari, and H. R. Harris, “Datapath system for multiple electron beam lithography systems using image compression,” Journal of Micro/Nanolithography, MEMS, and MOEMS, vol. 12, no. 3, p. 033018, 2013. [41] S. A. Savari, “An information theoretic perspective on e-beam directwrite as complementary lithography,” Journal of Vacuum Science Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, vol. 32, no. 6, 2014. [42] F. Krecinic, S.-J. Lin, and J. J. H. Chen, “Data path development for multiple electron beam maskless lithography,” Proc. SPIE, vol. 7970, p. 797010, 2011. [43] Jacob Ziv et al., 'A Universal Algorithm for Sequential Data Compression'. IEEE Trans Inf Theory, vol. IT-23, no. 3, 1977. [44] M.-B. Lin, J.-F. Lee, and G. E. Jan, “A lossless data compression and decompression algorithm and its hardware architecture,” IEEE Trans. Very Large Scale Integration Systems, vol. 14, no. 9, pp. 925–936, 2006. [45] Shao-Yun Fang, Iou-Jen Liu, and Yao-Wen Chang, “Stitch-Aware Routing for Multiple E-Beam Lithography,” DAC’13, 2013. [46] ITRS roadmap 2013: http://www.itrs.net/ [47] Paul Petric et al., “New advances with REBL for maskless highthroughput EBDW lithography,” Proc. SPIE, vol. 7970, p. 797018, 2011. [48] D. Brooks, V. Tiwari, and M. Martonosi, “Wattch: A framework for architectural-level power analysis and optimization,” in Proceedings of the 27th International Symposium on Computer Architecture (ISCA), Vancouver, British Columbia, Jun 2000. [49] N. K. Choudhary, S. V. Wadhavkar et al., “Fabscalar: Composing synthesizable rtl designs of arbitrary cores within a canonical superscalar template,” ACM SIGARCH Computer Architecture News, vol. 39, no. 3, pp. 11-22, 2011. [50] “HP labs. CACTI. http://www.hpl.hp.com/research/cacti/.” [51] Austin, Todd, Eric Larson, and Dan Ernst. 'SimpleScalar: An infrastructure for computer system modeling,' Computer, vol. 35, no. 2, pp. 59-67, 2002. [52] Chun-Chang Yu, Yu Hen Hu, Yi-Chang Lu, and Charlie Chung-Ping Chen, “Power Reduction of a Set-Associative Instruction Cache Using a Dynamic Early Tag Lookup,” in 2021 Design, Automation Test in Europe Conference Exhibition (DATE), IEEE, Jan. 2021. [53] Chun-Chang Yu, Pei-Chun Lin, Yi-Chang Lu, Charlie Chung-Ping Chen, “Cost-effective and channel-scalable hardware decoders for multiple electron-beam direct-write systems,” Journal of Micro/Nanolithography, MEMS, and MOEMS, vol. 17, p. 031202, Aug 2018. [54] EMMBC: https://www.eembc.org/ [55] Mittal, Sparsh. 'A survey of techniques for dynamic branch prediction,' in Concurrency and Computation: Practice and Experience, vol. 31, no. 1, p. e4666, 2019. [56] Skadron, Kevin, Margaret Martonosi, and D. Clark. 'Speculative updates of local and global branch history: A quantitative analysis,' Journal of Instruction-Level Parallelism, vol. 2, pp. 380-391, 2000. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19731 | - |
dc.description.abstract | 此論文提出了一種節能,低成本的指令快取記憶體查找技術,稱為動態早期標籤查找(DETL)的方法。DETL利用閒置的週期對快取記憶體的索引執行早期的標籤查找。提早獲得配對記憶體的資訊,可以節省用於並行存取其他快取記憶體的動態功耗。我們在RISC-V微結構中的四路集關聯指令快取記憶體上實現 DETL,並使用SPEC CPU2006基準套件測試其性能。我們觀察到動態功耗降低 19.38%,而成本增加不到 0.1%。 數據流量是多電子束直寫(MEBDW)系統中的一項關鍵指標,因此需要高效能的數據處理設備。主要的挑戰是如何通過具有成本效益的技術來實現高性能。此論文提出了一種高壓縮率的數據傳輸演算法和高速解壓縮的硬體實現方法,以提高系統的數據流量。硬體解碼器使用管道體系結構,運用長度編碼先進先出(FIFO)暫存陣列和並行調度邏輯來提高數據流量。該解碼器在FPGA上進行評估,並使用此論文提出的壓縮演算法所壓縮的佈局圖像進行模擬。結果顯示,與以前的方法相比,在類似的硬體成本下,壓縮率提高了 18.2%,數據流量提高了 254.8%。由於在設計中不使用靜態隨機存取記憶體(SRAM),因此可以輕鬆擴展系統的通道數,這使下一代MEBDW系統有可能實現更高的每小時晶圓(WPH)製造目標。 | zh_TW |
dc.description.abstract | Power consumption is the most important issue of modern processors. Instruction fetch activity cooperating with instruction cache is an energy hot spot. Dynamic power reduction in instruction cache lookup can contribute to the improvement of energy efficiency in processors. An energy-efficient and low area-overhead instruction cache lookup technique called Dynamic Early Tag Lookup (DETL) is proposed. DETL exploits a fetch bubble cycle to perform an early tag lookup for the index of the matching cache set. Therefore, the dynamic energy for parallel accesses of other cache memory banks may be saved. We implement DETL on a four-way set-associative I-cache in a RISC-V micro-architecture, and test its performance using the SPEC CPU2006 benchmark suite. We observed a 19.38% dynamic power reduction with < 0.1% area overhead. Data throughput is a critical metric in a Multiple Electron-Beam Direct-Write (MEBDW) system so that heavy-duty data processing equipment is required. The main challenge is about how to achieve high performance with cost-effective techniques. In this dissertation, we propose a high compression rate algorithm for efficient data transfer and high-speed decompression hardware to raise data throughput of the system. The hardware decoder uses pipeline architecture, a run-length encoding First-In-First-Out (FIFO) queue, and parallel dispatch logic to increase the throughput. The decoder is evaluated on Field-Programmable Gate Array (FPGA) and simulated with layout images that are compressed using our proposed compression software. The results demonstrate 18.2% better compression rate and 254.8% better throughput than the previous work with similar hardware cost. Because no Static Random-Access Memory (SRAM) is used in the design, the channel number of the system can be easily scaled up, which makes it possible for the next-generation MEBDW system to achieve higher Wafer Per Hour (WPH) targets. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T02:15:54Z (GMT). No. of bitstreams: 1 U0001-0602202100024700.pdf: 2640688 bytes, checksum: 4b74d78514a3281738dbd04d5e08bbcf (MD5) Previous issue date: 2021 | en |
dc.description.tableofcontents | 誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS v LIST OF FIGURES vii LIST OF TABLES ix Chapter 1 Introduction 1 1.1 Dynamic Power Reduction in Instruction Cache Lookup 1 1.2 High Throughput Decoder in Multiple Electron-Beam Direct-Write Systems 4 Chapter 2 Dynamically Early Tag Lookup 9 2.1 Related Works 9 2.2 Proposed Method and Implementation 10 2.2.1 Opportunity for Early Tag Lookup 10 2.2.2 Implementation of DETL in I-Cache 14 2.2.3 Look-Ahead Prediction PC 18 2.3 Experimental Results 21 2.3.1 Methodology 21 2.3.2 Results 25 2.3.3 Overhead 28 2.3.4 Comparison 29 Chapter 3 Cost-Effective and Channel-Scalable Hardware Decoders for MEBDW Systems 32 3.1 Related Works 32 3.2 Proposed Algorithm 34 3.2.1 LZOO Compression Algorithm 34 3.2.2 Modified LZ77 35 3.2.3 Offset Omission 36 3.2.4 Duplicate Line 38 3.2.5 Huffman-Like Coding 39 3.3 Proposed Hardware Decoder 41 3.3.1 Datapath 41 3.3.2 Micro-Architecture 42 3.3.3 Dataflow and Throughput 48 3.4 Experimental Results 51 3.4.1 Compression Rate of EBDW Encoder 51 3.4.2 Data Throughput of EBDW Decoder 52 3.4.3 Hardware Cost of EBDW Decoder 55 Chapter 4 Conclusion 57 4.1 Dynamic Power Reduction in Instruction Cache Lookup 57 4.2 High Throughput Decoder in Multiple Electron-Beam Direct-Write Systems 58 REFERENCE 59 | |
dc.language.iso | en | |
dc.title | 低功耗指令快取記憶體與高成本效益的電子束直寫系統之解碼器 | zh_TW |
dc.title | Low Power Instruction Cache and Cost-Effective Decoder of Electron-Beam Direct-Write Systems | en |
dc.type | Thesis | |
dc.date.schoolyear | 109-1 | |
dc.description.degree | 博士 | |
dc.contributor.oralexamcommittee | 盧奕璋(Yi-Chang Lu),方邵云(Shao-Yun Fang),陳少傑(Sao-Jie Chen),蔡坤諭(Kuen-Yu Tsai) | |
dc.subject.keyword | 動態早期標籤查找,降低動態功耗,節能處理器,關聯指令緩存,多電子束直寫,數據壓縮,硬體解碼器, | zh_TW |
dc.subject.keyword | dynamic early tag lookup,energy-efficient,instruction cache,multiple electron-beam direct-write,hardware decoder,data compression, | en |
dc.relation.page | 65 | |
dc.identifier.doi | 10.6342/NTU202100624 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2021-02-08 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
U0001-0602202100024700.pdf 目前未授權公開取用 | 2.58 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。