請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19618完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林宗賢(Tsung-Hsien Lin) | |
| dc.contributor.author | Cheng-Hui Wu | en |
| dc.contributor.author | 吳政輝 | zh_TW |
| dc.date.accessioned | 2021-06-08T02:08:54Z | - |
| dc.date.copyright | 2016-02-15 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-01-29 | |
| dc.identifier.citation | [1] E. A. Burton et al., 'FIVR — Fully integrated voltage regulators on 4th generation Intel® Core™ SoCs,' in Applied Power Electronics Conference and Exposition (APEC), 2014 Twenty-Ninth Annual IEEE, pp.432-439, March 2014.
[2] T. Y. Man, P. K. T. Mok, and M. Chan, “A high slew-rate push-pull output amplifier for low-quiescent current low-dropout regulators with transient-response improvement,” IEEE Trans. Circuits Syst. II., vol. 54, no. 9, pp. 755–759, Sep. 2007. [3] Available : https://en.wikipedia.org/wiki/5G [4] “Power Topology – Buck Converter,” Texas Instruments, Inc. [Online]. Available: www.ti.com/lit/an/slva432/slva432.pdf [5] P. Y. Wu, S. Y. S. Tsui, and P. K. T. Mok, “Area- and power-efficient monolithic buck converters with pseudo-type III compensation,” IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1446–1455, Aug. 2010. [6] M. Siu, P. K. T. Mok, K. N. Leung, Y. H. Lam, and W. H. Ki, “A voltage mode PWM buck regulator with end-point prediction,” IEEE Trans. Circuit Syst. II., vol. 53, no. 4, pp. 294-298, Apr. 2006. [7] M. Du and H. Lee, “An integrated speed- and accuracy-enhanced CMOS current sensor with dynamically-biased shunt feedback for current-mode buck regulators,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 10, pp. 2804–2814, Oct. 2010. [8] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics. Norwell, MA: Kluwer, 2001. [9] C. F. Lee and P. K. T. Mok, “A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 3–14, Jan. 2004. [10] S. Lee, S. Jung, J. Huh, C. Park, C. T. Rim, and G. H. Cho, “Robust and efficient synchronous buck converter with near-optimal dead-time control,” IEEE Int. Solid-State Circuits Conf., pp. 392–394, Feb. 2011. [11] Y. Gao, S. Zhang, Y. Xu, S. Gao, “Analysis and Comparison of Three Implementation Methodologies for High-Resolution DPWM,” Power Electronics Systems and Applications 2009. 3rd International Conference on., pp. 1-7, May 2009. [12] A.V. Peterchev, S.R. Sanders, “Quantization resolution and limit cycling in digitally controlled PWM converters”, IEEE Trans. on Power Electronics, vol. 18, no. 1, pp. 301-308, Jan. 2003. [13] B. J. Patella, A. Prodic, A. Zirger, D. Maksimovic, “High-frequency digital PWM controller IC for DC-DC converter,” IEEE Transactions on Power Electronics. vo1.18, no.1, pp. 43-46, Jan. 2003. [14] Available : https://en.wikipedia.org/wiki/Flip-flop_(electronics) [15] E. G. Soenen, A. Roth, J. Shi, M. Kinyua, J. Gaither, and E. Ortynska, “A robust digital DC-DC converter with rail-to-rail output range in 40nm CMOS,” IEEE Int. Solid-State Circuits Conf., pp. 198–199, Feb. 2010. [16] S.-Y. Park, J. Cho, K. Lee, E. Yoon, “PWM Buck Converter with >80% PCE in 45μA-to-4mA Loads Using Analog-Digital Hybrid Control for Implantable Biomedical Systems,” IEEE Int. Solid-State Circuits Conf., pp. 218-220, Feb. 2015. [17] P.H. Chen, C.S. Wu, K.C. Lin, “A 50nW-to-10mW Output Power Tri-Mode Digital Buck Converter with Self-Tracking Zero Current Detection for Photovoltaic Energy Harvesting,” IEEE Int. Solid-State Circuits Conf., pp. 376-378, Feb. 2015. [18] C. Huang and P. K. T. Mok, “A 100 MHz 82.4% efficiency package-bondwire based four-phase fully-integrated buck converter with flying capacitor for area reduction,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 2977–2988, Dec. 2013. [19] V. Kratyuk, P. K. Hanumolu, U. Moon, and K. Mayaram, “A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy,” IEEE Trans. Circuits Syst. II, vol. 54, no. 5, pp. 247–251, Mar. 2007. [20] H. Q. Li, S. L. Wang, Y. Gao, Y. Song, L. Geng, “A Flash Window ADC for DVS-enabled Digital Controlled DC–DC Converters,” IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1-3, Oct. 2012. [21] H. Huang, K. Chen, and S. Kuo, “Dithering skip modulation, width and dead time controllers in highly efficient DC-DC converters for system-on-chip applications,” IEEE J. Solid-State Circuits, vol. 42, no.11, pp. 2451- 2465, Nov. 2007. [22] M. Du, H. Lee, and J. Liu, “A 5-MHz 91% peak-power-efficiency buck regulator with auto-selectable peak-and vally-current control,” IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1928–1939, Aug. 2011. [23] J.-J. Chen, M.-X. Lu, T.-H. Wu, and Y.-S. Hwang, “Sub-1-V fast response hysteresis-controlled CMOS buck converter using adaptive ramp techniques,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 9, pp. 1608–1618, Sep. 2013. [24] T.Y. Man, P.K.T. Mok, M. Chan, “An Auto-Selectable-Frequency Pulse-Width Modulator for Buck Converters with Improved Light-Load Efficiency,” IEEE Int. Solid-State Circuits Conf., pp. 440-441, Feb. 2008. [25] P. Li, D. Bhatia, L. Xue, and R. Bashirullah, “A 90–240 MHz hysteretic controlled DC-DC buck converter with digital phase locked loop synchronization,” IEEE J. Solid-State Circuits, vol. 46, no. 9, pp. 2108– 2119, Sep. 2011. [26] S. Musunuri and P. L. Chapman, “Improvement of light-load efficiency using width-switching scheme for CMOS transistors,” IEEE Power Electron. Lett., vol. 3, no. 3, pp. 105–110, Sep. 2005. [27] K.-I. Wu, S.-H. Hung, S.-Y. Shieh, B.-T. Hwang, C.-P. Chen, “Current-Mode Adaptively Hysteretic Control for Buck Converters with Fast Transient Response and Improved Output Regulation,” IEEE International Symposium on Circuits and Systems, pp. 950–953, Jun. 2014. [28] Z. Sun, L. Siek, R.-P, Singh, M. Je “A Fixed-frequency Hysteretic Controlled Buck DC-DC Converter with Improved Load Regulation,” IEEE International Symposium on Circuits and Systems, pp. 954-957, Jun. 2014. [29] H. H. Ahmad, B. Bakkaloglu, “A 300mA 14mV-Ripple Digitally Controlled Buck Converter Using Frequency Domain ΔΣ ADC and Hybrid PWM Generator,” IEEE Int. Solid-State Circuits Conf., pp. 202-203, Feb. 2010. [30] Gangopadhyay S, Somasekhar D, Tschanz J.W, Raychowdhury A, “A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits,” IEEE J. Solid-State Circuits, vol. 49, no. 11, pp.2684 – 2693, Oct. 2014. [31] Peter H, Tanay K, Bradley A.B, Colleen P, David F, Shekhar B, “Area-Efficient Linear Regulator With Ultra-Fast Load Regulation,” IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 933 – 940, Apr. 2005. [32] P. Y. Or and K. N. Leung, “An output-capacitorless low-dropout regulator with direct voltage-spike detection,” IEEE J. Solid-State Circuits, vol. 45, no. 2, pp. 458–466, Feb. 2010. [33] C. K. Chava and J. Silva-Martinez, “A frequency compensation scheme for LDO voltage regulators,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 1, pp. 1041–1050, Jun. 2004. [34] Y.-H. Lam and W.-H. Ki, “A 0.9 V 0.35 um adaptively biased CMOS LDO regulator with fast transient response,” IEEE Int. Solid-State Circuits Conf., pp. 442–443, Feb. 2008. [35] X. Zhang, P. -H, Chen, et. al. , “A 0.6 V Input CCM/DCM Operating Digital Buck Converter in 40 nm CMOS,” IEEE J. Solid-State Circuits, vol. 49, no. 11, pp. 2377-2386, Nov. 2014. [36] M. P. Chan and P. K. T. Mok, “Fully integrated digital controller IC for buck converter with a differential-sensing ADC,” IEEE Int. Conf. on Electron Devices and Solid-State Circuits, pp. 1–4, Dec. 2008. [37] Rahman. N, Parayandeh. A, Wang. K, Prodic. A, “Multimode digital SMPS controller IC for low-power management,” IEEE International Symposium on Circuits and Systems, pp. 5327–5330, May 2006. [38] T. Liu, H. Yeom, B. Vermeire, P. Adell, B. Bakkaloglu, “A Digitally Controlled DC-DC Buck Converter with Lossless Load-Current Sensing and BIST Functionality,” IEEE Int. Solid-State Circuits Conf., pp. 388-390, Feb. 2011. [39] S. Bandyopadhyay, Y. K. Ramadass, A. P. Chandrakasan, “20μA to 100mA DC-DC Converter with 2.8 to 4.2V Battery Supply for Portable Applications in 45nm CMOS,” IEEE Int. Solid-State Circuits Conf., pp. 386-388, Feb. 2011. [40] M. K. Alghandi, A. A. Hamoui, “A Spurious-Free Switching Buck Converter Achieving Enhanced Light-Load Efficiency By Using a ΔΣ-Modulator Controller With a Scalable Sampling Frequency,” IEEE J. Solid-State Circuits, vol. 47, no. 4, pp. 841–851, Apr. 2012. [41] C.-S. Wu, K.-C. Lin, Y.-P. Kuo, P.-H. Chen, Y.-H. Chu, and W. Hwang “An All-Digital Power Management Unit with 90% Power Efficiency and ns-order Voltage Transition Time for DVS Operation in Low Power Sensing SoC Applications,” IEEE International Symposium on Circuits and Systems, pp. 1370–1373, May 2015. [42] Okuma, Y., et al., “0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS,” IEEE Custom Integrated Circuits Conference (CICC), pp. 1 – 4, Sep. 2010. [43] C. Huang, L. Cheng, P. K. T. Mok and W. -Hung. Ki, “High-Side NMOS Power Switch and Bootstrap Driver for High-Frequency Fully-Integrated Converters with Enhanced Efficiency,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 693 – 696, May 2013. [44] M. P. Chan and P. K. T. Mok, “On-chip digital inductor current sensor for monolithic digitally controlled DC-DC converters,” in Proc. IEEE Int. Symp. Circuits Syst., pp. 962–965, May 2012. [45] P.-H. Chen, C.-S. Wu, and K.-C. Lin, “A 50nW-to-10mW Output Power Tri-Mode Digital Buck Converter with Self-Tracking Zero Current Detection for Photovoltaic Energy Harvesting,” IEEE J. Solid-State Circuits, vol. PP, pp. 1-10, Jan. 2016. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19618 | - |
| dc.description.abstract | 在一個積體電路系統中，電源管理晶片扮演了相當重要的角色，其負責提供一個穩定的電壓源，一個理想上不隨電池電壓或是輸出電流而有所變化的電壓源；然而，電源管理晶片所需的外掛電感以及電容，佔據了相當大的使用空間。本論文提出兩種微小型電源轉換器，用以減小外掛元件的數量以及大小。
第一個作品利用電流操控模式特有的單極點特性，以及提高操作的頻率，不僅將補償器的外掛元件數量減少至一個，更將所需之元件數值減小。另外，藉由提升轉導的瞬態率以及內建軟啟動機制，分別將暫態響應速率提升三十倍，以及消除電路啟動時不穩定的狀態。在兩千萬赫茲的操作頻率下，本作品使用兩百四十奈米亨利的電感及兩百二十奈米法拉的電容，輸入電壓為一點二伏特，輸出電壓為零點九伏特，實現一能源轉換效率達百分之七十三點五的微小型基於電感之高切換頻率降壓型直流對直流電源轉換器。 第二個作品利用數位控制的方式，將補償器外掛元件完全移除以外，更使用所提出之二進制權延遲線數位脈衝寬度調變器，將原本六十四轉一數據選擇器的面積節省下來。四位元窗型快閃類比數位轉換器有效節省百分之八十七點五的能源消耗及面積，並且將類比數位轉換器的延遲時間減至最低。在五千萬赫茲的操作頻率下，本作品使用一百奈米亨利的電感及一百奈米法拉的電容，輸入電壓為一點二伏特，輸出電壓為零點八伏特，實現一能源轉換效率高達百分之八十一的微小型基於電感之數位控制高切換頻率降壓型直流對直流電源轉換器。 | zh_TW |
| dc.description.abstract | Power management IC (PMIC) is a critical building block in integrated circuits for providing stable supply voltages, which ideally don’t change with the battery voltage and the output load current. However, due to the limited area, large inductors and capacitors used in the PMICs are not preferred in modern portable devices. In this thesis, two compact dc-dc power converters are proposed to minimize the off-chip component sizes with different controller types.
In the first work, an inductor-based high-switching frequency current-controlled step-down dc-dc power converter is proposed to reduce the off-chip component sizes. With the inherent one pole characteristic, only one additional off-chip capacitor is used. The slew-rate enhanced g_m stage is designed to improve the transient response by 30X faster while the soft-start circuit is employed to prevent ambiguity when circuit turns on. Operating at 20 MHz switching frequency, a compact dc-dc power converter is realized with 240 nH inductor and 220 nF capacitor and the power conversion efficiency is as high as 73.5 %. In the second work, an inductor-based high-switching frequency digital-controlled step-down dc-dc power converter with weighted delay-line DPWM is proposed to further reduce the off-chip component sizes. A 4-bit window-flash ADC is employed to save 87.5 % of the power and area and minimize the ADC latency. Meanwhile, the proposed weighted delay-line DPWM successfully converts the digital code into time-domain duty cycle information without the redundant 64-to-1 MUX. Operating at 50 MHz switching frequency, a compact dc-dc power converter is realized with 100 nH inductor and 100 nF capacitor and the power conversion efficiency is over 80 % for load current ranges from 350 mA to 550 mA. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T02:08:54Z (GMT). No. of bitstreams: 1 ntu-105-R02943022-1.pdf: 5175909 bytes, checksum: ef9dde9f3710ab5c3f71cc1f72734de1 (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | Chapter 1 Introduction 1
1.1 Introduction to Power Management IC 1 1.2 Motivation 3 1.3 Thesis Overview 5 Chapter 2 Fundamentals of Inductor-Based DC-DC Power Converter 7 2.1 A Brief Overview of Inductor-Based DC-DC Power Converter 7 2.1.1 Theory of Operation 7 2.1.2 Steady-State Converter Analysis 11 2.1.3 Calculation of Output Voltage Ripple 18 2.2 System Stability Analysis 21 2.2.1 Circuit Modeling 21 2.2.2 Control-To-Output Transfer Function Gvd(s) 23 2.2.3 Pulse-Width Modulator Transfer Function GPWM(s) 25 2.2.4 Compensator Transfer Function GC(s) 27 2.3 Summary 37 Chapter 3 Design and Implementation of Inductor-Based High-Switching Frequency Current-Controlled Step-Down DC-DC Power Converter 40 3.1 Introduction to the Main Idea 40 3.2 System Design 42 3.2.1 Current-Controlled Method 42 3.2.2 Sub-harmonic Oscillation 44 3.3 Circuit Implementation 50 3.3.1 System Stability and Compensator 50 3.3.2 Slew-Rate enhanced gm Stage 55 3.3.3 Current Sensing Circuit 57 3.3.4 Soft-Start 58 3.4 Simulation Results 60 3.5 Experimental Results 64 3.5.1 Testing Setup 65 3.5.2 Measurement Results 66 Chapter 4 Design and Implementation of Inductor-Based High-Switching Frequency Digital-Controlled Step-Down DC-DC Power Converter with Weighted Delay-Line DPWM 80 4.1 Motivation 80 4.2 System Design 81 4.2.1 Digital-Controlled Method 81 4.2.2 Limit-Cycle Oscillation 82 4.3 Circuit Implementation 84 4.3.1 System Stability and Compensator 85 4.3.2 Window-Flash ADC 91 4.3.3 Weighted Delay-Line DPWM 93 4.4 Simulation Results 97 Chapter 5 Conclusions and Future Works 104 5.1 Conclusions 104 5.2 Future Works 105 References 108 | |
| dc.language.iso | en | |
| dc.title | 基於電感之高切換頻率降壓型直流對直流電源轉換器設計 | zh_TW |
| dc.title | Design of Inductor-Based High-Switching Frequency Step-Down DC-DC Power Converters | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 104-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉深淵(Shen-Yuan Liu),黃柏鈞(Po-Chun Huang),許孟烈(Meng-Lieh Hsu),黃育賢(Yu-Hsien Huang) | |
| dc.subject.keyword | 高切換頻率,降壓,直流對直流,電源轉換器, | zh_TW |
| dc.subject.keyword | high-switching frequency,DC-DC,power converter,buck, | en |
| dc.relation.page | 114 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2016-01-29 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-105-1.pdf 目前未授權公開取用 | 5.05 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。