請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19609完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李坤彥(Kung-Yen Lee) | |
| dc.contributor.author | Yun-Kai Lai | en |
| dc.contributor.author | 賴云凱 | zh_TW |
| dc.date.accessioned | 2021-06-08T02:08:21Z | - |
| dc.date.copyright | 2020-08-24 | |
| dc.date.issued | 2020 | |
| dc.date.submitted | 2020-08-18 | |
| dc.identifier.citation | [1] H.-S. Lee, 'High power bipolar junction transistors in silicon carbide,' KTH, 2005. [2] S. Pearton et al., 'A review of Ga2O3 materials, processing, and devices,' Applied Physics Reviews, vol. 5, no. 1, p. 011301, 2018. [3] T. Kimoto, 'Material science and device physics in SiC technology for high-voltage power devices,' Japanese Journal of Applied Physics, vol. 54, no. 4, p. 040103, 2015. [4] R. N. Hall, 'Electron-hole recombination in germanium,' Physical review, vol. 87, no. 2, p. 387, 1952. [5] K. Dawon, 'Electric field controlled semiconductor device,' ed: Google Patents, 1963. [6] E. S. Oxner, FET technology and application. CRC Press, 1988. [7] Y. Tarui, 'Diffusion self-aligned MOST: A new approach for high speed device,' in Proc. 1st Conf. on Solid State Devices, Tokyo, 1969; Suppl. to Jpn. Society of Appl. Phys., 1970, vol. 39, pp. 105-110. [8] S. Shirota and S. Kaneda, 'Transient response of new type of varactor diode having multilayer structure,' Electronics Letters, vol. 14, no. 3, pp. 56-57, 1978. [9] X. Chen, 'Semiconductor power devices with alternating conductivity type high-voltage breakdown regions,' ed: Google Patents, 1993. [10] M. Matin, A. Saha, and J. A. Cooper, 'A self-aligned process for high-voltage, short-channel vertical DMOSFETs in 4H-SiC,' IEEE Transactions on Electron Devices, vol. 51, no. 10, pp. 1721-1725, 2004. [11] D. Okamoto, M. Sometani, S. Harada, R. Kosugi, Y. Yonezawa, and H. Yano, 'Improved channel mobility in 4H-SiC MOSFETs by boron passivation,' IEEE Electron Device Letters, vol. 35, no. 12, pp. 1176-1178, 2014. [12] K. Han, B. Baliga, and W. Sung, 'Split-gate 1.2-kV 4H-SiC MOSFET: Analysis and experimental validation,' IEEE Electron Device Letters, vol. 38, no. 10, pp. 1437-1440, 2017. [13] T. Kimoto, H. Kosugi, J. Suda, Y. Kanzaki, and H. Matsunami, 'Design and fabrication of RESURF MOSFETs on 4H-SiC (0001),(112~ 0), and 6H-SiC (0001),' IEEE transactions on electron devices, vol. 52, no. 1, pp. 112-117, 2004. [14] J. Wang et al., 'Characterization, modeling, and application of 10-kV SiC MOSFET,' IEEE Transactions on Electron Devices, vol. 55, no. 8, pp. 1798-1806, 2008. [15] Z. Chen, Y. Yao, D. Boroyevich, K. D. Ngo, P. Mattavelli, and K. Rajashekara, 'A 1200-V, 60-A SiC MOSFET multichip phase-leg module for high-temperature, high-frequency applications,' IEEE Transactions on Power Electronics, vol. 29, no. 5, pp. 2307-2320, 2013. [16] L. Cheng et al., '3300 V, 30 A 4H-SiC Power DMOSFETs,' in 2009 International Semiconductor Device Research Symposium, 2009, pp. 1-2: IEEE. [17] A. Bolotnikov et al., '3.3 kV SiC MOSFETs designed for low on-resistance and fast switching,' in 2012 24th International Symposium on Power Semiconductor Devices and ICs, 2012, pp. 389-392: IEEE. [18] X. Huang, L. Vursin, A. Bhalla, W. Simon, and J. C. Dries, 'Design and fabrication of 3.3 KV SiC MOSFETs for industrial applications,' in 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD), 2017, pp. 255-258: IEEE. [19] B. J. Baliga, Fundamentals of power semiconductor devices. Springer Science Business Media, 2010. [20] M. S. Adler, K. W. Owyang, B. J. Baliga, and R. A. Kokosa, 'The evolution of power device technology,' IEEE Transactions on Electron Devices, vol. 31, no. 11, pp. 1570-1591, 1984. [21] J. W. Palmour, C. Carter, J. Edmund, and H.-S. Kong, '6H-silicon carbide power devices for aerospace applications,' in Intersociety Energy Conversion Engineering Conference, 1993, vol. 1, pp. 1.249-1.249: AMERICAN NUCLEAR SOCIETY. [22] L. Chang, S. Tang, T.-J. King, J. Bokor, and C. Hu, 'Gate length scaling and threshold voltage control of double-gate MOSFETs,' in International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No. 00CH37138), 2000, pp. 719-722: IEEE. [23] I. Polishchuk and C. Hu, 'Polycrystalline silicon/metal stacked gate for threshold voltage control in metal–oxide–semiconductor field-effect transistors,' Applied Physics Letters, vol. 76, no. 14, pp. 1938-1940, 2000. [24] S. Sun and J. D. Plummer, 'Modeling of the on-resistance of LDMOS, VDMOS, and VMOS power transistors,' IEEE Transactions on Electron Devices, vol. 27, no. 2, pp. 356-367, 1980. [25] J. H. Hohl and K. F. Galloway, 'Analytical model for single event burnout of power MOSFETs,' IEEE Transactions on Nuclear Science, vol. 34, no. 6, pp. 1275-1280, 1987. [26] D. A. Neamen, Semiconductor physics and devices: basic principles. New York, NY: McGraw-Hill, 2012. [27] A. W. Ludikhuize, 'A review of RESURF technology,' in 12th International Symposium on Power Semiconductor Devices ICs. Proceedings (Cat. No. 00CH37094), 2000, pp. 11-18: IEEE. [28] S. Yamauchi, T. Shibata, S. Nogami, T. Yamaoka, Y. Hattori, and H. Yamaguchi, '200V super junction MOSFET fabricated by high aspect ratio trench filling,' in 2006 IEEE International Symposium on Power Semiconductor Devices and IC's, 2006, pp. 1-4: IEEE. [29] J. Sakakibara, Y. Noda, T. Shibata, S. Nogami, T. Yamaoka, and H. Yamaguchi, '600V-class super junction MOSFET with high aspect ratio P/N columns structure,' in 2008 20th International Symposium on Power Semiconductor Devices and IC's, 2008, pp. 299-302: IEEE. [30] P. N. Kondekar, H.-S. Oh, and Y.-B. Kim, 'Study of the degradation of the breakdown voltage of a super-junction power MOSFET due to charge imbalance,' Journal of the Korean Physical Society, vol. 48, no. 4, pp. 624-630, 2006. [31] B. Liang, F.-s. Yang, Z. Ding, and X.-h. Fu, 'Simulation and analysis of the breakdown mechanism and characteristics of super junction structure,' in 2011 International Conference on Electronics, Communications and Control (ICECC), 2011, pp. 467-470: IEEE. [32] W. Saito, 'Theoretical limits of superjunction considering with charge imbalance margin,' in 2015 IEEE 27th International Symposium on Power Semiconductor Devices IC's (ISPSD), 2015, pp. 125-128: IEEE. [33] Y. Onishi, S. Iwamoto, T. Sato, T. Nagaoka, K. Ueno, and T. Fujihira, 'mΩcm2 680 V silicon superjunction MOSFET,” Power Semiconductor Devices and ICs, 2002,' in Proceedings of the 14th International Symposium on, vol, vol. 241, p. 2002. [34] W. Cai-Lin and S. Jun, 'An oxide filled extended trench gate super junction MOSFET structure,' Chinese Physics B, vol. 18, no. 3, p. 1231, 2009. [35] R. Kosugi et al., 'Development of SiC super-junction (SJ) device by deep trench-filling epitaxial growth,' in Materials Science Forum, 2013, vol. 740, pp. 785-788: Trans Tech Publ. [36] T. Masuda, Y. Saito, T. Kumazawa, T. Hatayama, and S. Harada, '0.63 mΩcm2/1170 V 4H-SiC super junction V-groove trench MOSFET,' IEEE IEDM Tech. Dig, pp. 177-180, 2018. [37] W. Sung and B. J. Baliga, 'A comparative study 4500-V edge termination techniques for SiC devices,' IEEE Transactions on Electron Devices, vol. 64, no. 4, pp. 1647-1652, 2017. [38] J.-Y. Jiang, H.-C. Hsu, K.-W. Chu, C.-F. Huang, and F. Zhao, 'Experimental study of counter-doped junction termination extension for 4H–SiC power devices,' IEEE Electron Device Letters, vol. 36, no. 7, pp. 699-701, 2015. [39] T. Hatakeyama, J. Nishio, C. Ota, and T. Shinohe, 'Physical modeling and scaling properties of 4H-SiC power devices,' in 2005 International Conference On Simulation of Semiconductor Processes and Devices, 2005, pp. 171-174: IEEE. [40] A. Chynoweth, 'Ionization rates for electrons and holes in silicon,' physical review, vol. 109, no. 5, p. 1537, 1958. [41] A. Ortiz-Conde, F. G. Sánchez, J. J. Liou, A. Cerdeira, M. Estrada, and Y. Yue, 'A review of recent MOSFET threshold voltage extraction methods,' Microelectronics reliability, vol. 42, no. 4-5, pp. 583-596, 2002. [42] A. Q. Huang, 'New unipolar switching power device figures of merit,' IEEE Electron Device Letters, vol. 25, no. 5, pp. 298-301, 2004. [43] 林丹晳, '3.3 kV 級 4H 碳化矽垂直型金氧半場效電晶體性能及未箝制電感切換模擬研究,' 國立清華大學, 2018. [44] W. Sung, A. Q. Huang, and B. J. Baliga, 'Bevel junction termination extension—A new edge termination technique for 4H-SiC high-voltage devices,' IEEE Electron Device Letters, vol. 36, no. 6, pp. 594-596, 2015. [45] W. Sung, E. Van Brunt, B. Baliga, and A. Q. Huang, 'A new edge termination technique for high-voltage devices in 4H-SiC–multiple-floating-zone junction termination extension,' IEEE electron device letters, vol. 32, no. 7, pp. 880-882, 2011. [46] H. Miyake, T. Okuda, H. Niwa, T. Kimoto, and J. Suda, '21-kV SiC BJTs with space-modulated junction termination extension,' IEEE Electron Device Letters, vol. 33, no. 11, pp. 1598-1600, 2012. [47] D. Alok, B. Baliga, and P. McLarty, 'A simple edge termination for silicon carbide devices with nearly ideal breakdown voltage,' IEEE Electron Device Letters, vol. 15, no. 10, pp. 394-395, 1994. [48] G. Feng, J. Suda, and T. Kimoto, 'Space-modulated junction termination extension for ultrahigh-voltage pin diodes in 4H-SiC,' IEEE transactions on electron devices, vol. 59, no. 2, pp. 414-418, 2011. [49] Y. Huang, Y. Wang, X. Kuang, W. Wang, J. Tang, and Y. Sun, 'Step-double-zone-JTE for SiC devices with increased tolerance to JTE dose and surface charges,' Micromachines, vol. 9, no. 12, p. 610, 2018. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19609 | - |
| dc.description.abstract | 在本篇論文中，將透過TCAD Sentaurus軟體進行3.3 kV 4H-SiC Quasi-SJ VD MOSFET主動區設計以及3.3 kV 4H-SiC VD MOSFET終端區設計。在3.3kV 4H-SiC Quasi-SJ VD MOSFET主動區設計中，符合國內半導體代工廠的製程限制，將磊晶層中加入3根浮動式P型結構。每一根浮動式P型結構加入後，對浮動式P型結構的濃度、光罩開口寬度以及元件磊晶厚度進行優化設計，並採用電流擴散層(Current Spreading Layer, CSL)及混合磊晶層的技術；優化設計後的3.3kV 4H-SiC Quasi-SJ VD MOSFET主動區，在逆向偏壓下，擁有相當好的電壓承受能力，維持一定的崩潰電壓值，且在順向導通部分，能夠擁有比Conventional 4H-SiC VD MOSFET更低的導通電阻值，特徵導通電阻為6.47 mΩ∙cm^2。 在3.3 kV 4H-SiC VD MOSFET終端區設計中，採用Double Zone JTE結構以及在JTE中加入P+ Rings結構，並進行優化。透過P+結構能使終端區結構在逆向偏壓下，電場分布均並向外延伸，提高耐壓能力。並加入外環設計，能提高在JTE劑量上偏差的50 %容忍度，使終端區結構的崩潰電壓值對JTE劑量變化不會有明顯大幅的下降。 | zh_TW |
| dc.description.abstract | In this thesis, the 3.3 kV 4H-SiC Quasi-SJ VD MOSFET cell region and the edge termination region are designed by using TCAD Sentaurus. In the 3.3 kV 4H-SiC Quasi-SJ VD MOSFET cell region, the three floating P structures are formed in the epitaxial layer, and optimized by adjusting width and doping concentration. Moreover, the current spreading layer and the multiple drift regions with doping concentrations are adopted in the structure. For the reverse characteristics, the 3.3 kV 4H-SiC Quasi-SJ VD MOSFET can withstand reverse voltage of 3.3 kV with low leakage current, achieving the target of this research. Additionally, for the forward characteristics, the structure owns lower on-resistance 6.47 mΩ∙cm^2 than that of a conventional 4H-SiC VD MOSFET. The double zone JTE structure and the P+ Rings structures are adopted in the 3.3 kV 4H-SiC VD MOSFET edge termination region. The P+ Rings structures in edge termination design can make electric field extend more widely and uniformly to increase the breakdown voltage, so that the highest BV is 3973 V. Furthermore, the JTE outer rings structure are adopted in the design, in order to increase JTE dose tolerance which ensures that the breakdown voltage of the edge termination can be maintained at same value in wider JTE dose range. The tolerance percentage increase 50 %. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T02:08:21Z (GMT). No. of bitstreams: 1 U0001-1608202008011100.pdf: 8672562 bytes, checksum: 8e9b4ce3d316a90aeede1b51cd916141 (MD5) Previous issue date: 2020 | en |
| dc.description.tableofcontents | 致謝(I) 中文摘要(II) Abstract(III) 目錄(IV) 圖目錄(VII) 表目錄(XII) 第一章 緒論(1) 1.1 前言(1) 1.2 碳化矽材料性質(2) 1.3 研究動機(4) 1.4 文獻回顧(5) 第二章 元件結構原理(7) 2.1 常見功率元件種類(7) 2.2 常見的垂直型功率金氧半場效電晶體結構(8) 2.2.1垂直式雙佈植金氧半場效電晶體的順向導通機制(11) 2.2.2垂直式雙佈植金氧半場效電晶體的逆向崩潰機制(14) 2.3 超接面(17) 2.3.1超接面的原理與結構(17) 2.3.2超接面的製程方法(20) 2.3.3 超接面應用於碳化矽金氧半場效電晶體(22) 2.4邊緣終端區結構(23) 2.4.1 終端區結構的重要性(23) 2.4.2常見終端區結構介紹(24) 第三章 模擬環境(28) 3.1模擬方法(28) 3.2物理模型(29) 第四章 金氧半場效電晶體模擬結果分析與討論(33) 4.1元件初步設計(33) 4.2 於磊晶層加入第一根浮動式P型結構 (版本一)(41) 4.2.1第一根浮動式P型結構濃度對於元件電性影響(43) 4.2.2 第一根浮動式P型結構深度對於元件電性影響(45) 4.2.3 第一根浮動式P型結構寬度對於元件電性影響(4)8 4.2.4 第一次磊晶厚度減少對於元件電性影響(51) 4.3 於磊晶層加入第二根浮動式P型結構(版本二)(53) 4.3.1 第二根浮動式P型結構濃度對於元件電性影響(54) 4.3.2 第二根浮動式P型結構寬度對於元件電性影響(57) 4.3.3 第二次磊晶厚度減少對於元件電性影響(60) 4.4 於磊晶層加入第三根浮動式P型結構(版本三)(62) 4.4.1 第三根浮動式P型結構濃度對於元件電性影響(62) 4.4.2 第三根浮動式P型結構寬度對於元件電性影響(67) 4.5 加入電流擴散層與混合磊晶層(版本四)(70) 4.5.1 電流擴散層(Current Spreading Layer, CSL)(70) 4.5.2 混合磊晶層(73) 4.6 整理與討論(79) 第五章 終端區結構模擬結果分析與討論(80) 5.1終端區初步設計(80) 5.2 JTE結構設計(85) 5.2.1 JTE結構劑量設計(85) 5.2.2 JTE長度設計(88) 5.3 新穎終端區結構設計(89) 5.3.1 JTE zone one區域劑量設計(90) 5.3.2 JTE zone two區域劑量設計(92) 5.3.3 P+ Rings結構加入終端區設計對於崩潰電壓影響(95) 5.3.4外環結構加入終端區設計對於崩潰電壓影響(100) 5.4 整理與討論(103) 第六章 結論與未來展望(104) 參考文獻(106) | |
| dc.language.iso | zh-TW | |
| dc.title | 3.3 kV 4H-SiC 準超接面金氧半場效電晶體與終端區結構設計 | zh_TW |
| dc.title | Design of 3.3 kV 4H-SiC Quasi-Super Junction Metal Oxide Semiconductor Field Effect Transistor and Edge Termination Structure | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 108-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 胡振國(Jenn-Gwo Hwu),黃智方(Chin-Fang Huang),李佳翰(Jia-Han Li) | |
| dc.subject.keyword | 4H-SiC,高功率金氧半場效電晶體,準超接面金氧半場效電晶體,垂直雙佈植金氧半場效電晶體,邊緣終端區保護結構,崩潰電壓,特徵導通電阻,接面延伸終端結構,保護環,接面延伸終端外環結構, | zh_TW |
| dc.subject.keyword | 4H-SiC,Power device,Quasi-SJ Power MOSFET,DMOSFET,Edge Termination,BV,Ron,sp,JTE,Guard Rings,JTE Outer Rings, | en |
| dc.relation.page | 109 | |
| dc.identifier.doi | 10.6342/NTU202003561 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2020-08-19 | |
| dc.contributor.author-college | 工學院 | zh_TW |
| dc.contributor.author-dept | 工程科學及海洋工程學研究所 | zh_TW |
| 顯示於系所單位： | 工程科學及海洋工程學系 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| U0001-1608202008011100.pdf 目前未授權公開取用 | 8.47 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。