請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19533完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃天偉(Tian-Wei Huang) | |
| dc.contributor.author | Shih-Jyun Luo | en |
| dc.contributor.author | 羅士竣 | zh_TW |
| dc.date.accessioned | 2021-06-08T02:03:58Z | - |
| dc.date.copyright | 2016-04-15 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-03-14 | |
| dc.identifier.citation | [1] Aoki, S. D. Kee, D. B. Rutledge and A. Hajimiri,'Distributed active transformer–a new power-combining and impedance-transformation technique',IEEE Trans. Microw. Theory Tech.,vol. 50,no. 1,pp.316 -331 2002.
[2] H. Dabag, B. Hanafi, F. Golcuk, A. Agah, J. Buckwalter, and P. Asbeck, “Analysis and design of stacked-FET millimeter-wave power amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 61, no. 4, pp. 1543–1556, Apr. 2013. [3] J. McRory, G. Rabjohn, and R. Johnston, “Transformer coupled stacked FET power amplifiers,” IEEE J. Solid-State Circuits, vol. 34, no. 2, pp. 157–161, Feb. 1999. [4] A. K. Ezzeddine and H. C. Huang, “The high voltage/high power FET (HiVP),” in Proc. IEEE Radio Freq. Integr. Circuits Symp., 2003, pp. 215–218. [5] M.-F. Lei, Z.-M. Tsai, K.-Y. Lin, and H. Wang, “Design and analysis of stacked power amplifier in series-input and series-output configuration,” IEEE Trans. Microw. Theory Techn., vol. 55, no. 12, pp. 2802–2812, Dec. 2007. [6] A. Agah, J. Jayamon, P. Asbeck, L. Larson, and J. Buckwalter, “Multi-driver stacked-FET power amplifiers at 90 GHz in 45 nm SOI CMOS,” IEEE J. Solid-State Circuits, vol. 49, no. 5, pp. 1148–1157, May 2014. [7] M. Bohsali and A. M. Niknejad, “Current combining 60 GHz CMOS power amplifiers,” in RFIC Symp., May 2009, pp. 31–34. [8] C. C. Hung, J. L. Kuo, K. Y. Lin, and H. Wang, “A 22.5-dB gain, 20.1-dBm output power K-band power amplifier in 0.18-um CMOS, ' IEEE RFIC Symp., pp. 557–560, May 2010. [9] C. Y. Law and A.-V. Pham, “A high-gain 60 GHz power amplifier with 20 dBm output power in 90 nm CMOS,” in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2010, pp. 426–427. [10] David M. Pozar, Microwave Engineering, 3rd Edition, John Wiley & Sons, Inc., Hoboken, New Jersey, 2005. [11] C. Y. Law and A.-V. Pham, “A high-gain 60 GHz power amplifier with 20 dBm output power in 90 nm CMOS,” in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2010, pp. 426–427. [12] C.-C. Kuo, Y.-H. Lin, H.-C. Lu, H. Wang, “A K-band compact fully integrated transformer power amplifier in 0.18-um CMOS,” in Microwave conference Proceedings(APMC), 2013, pp.579-599 [13] I. Aoki, S. Kee, D. Rutledge, and A. Hajimiri, “Fully integrated CMOS power amplifier design using the distributed active-transformer architecture,” IEEE J.Solid-State Circuits, vol. 37, no. 3, pp. 371–383, Mar. 2002. [14] J.-F. Yeh, J.-H. Tsai, and T.-W. Huang, “A 60-GHz power amplifierdesign using dual-radial symmetric architecture in 90-nm low-power CMOS,” IEEE Trans. Microw. Theory Tech., vol. 61, no. 3, pp.1280–1290, Mar. 2013. [15] U. R. Pfeiffer and D. Goren, “A 23 dBm 60-GHz distributed active transformer in a silicon process technology,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 5, pp. 857–865, May 2007. [16] Dixian Zhao and Patrick Reynaert, “An E-Band Power Amplifier With Broadband Parallel-Series Power Combiner in 40-nm CMOS,” IEEE Trans. Microw. Theory Tech., vol. 63, no. 2, pp. 683 - 690, Feb 2015. [17] K. H. An, O. Lee, H. Kim, D. H. Lee, J. Han, K. S. Yang, Y. Kim, J. J.Chang, W.Woo, C.-H. Lee, H. Kim, and J. Laskar, “Power-combining transformer techniques for fully-integrated CMOS power amplifiers,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1064–1075, May 2008. [18] K. H. An , O. Lee , H. Kim , D. H. Lee , J. Han , K. S. Yang , Y. Kim , J. J. Chang , W. Woo , C.-H. Lee , H. Kim and J. Laskar 'Power-combining transformer techniques for fully-integrated CMOS power amplifiers', IEEE J. Solid-State Circuits, vol. 43, no. 5, pp.1064 -1075, May 2008 [19] I. Aoki , S. Kee , R. Magoon , R. Aparicio , F. Bohn , J. Zachan , G. Hatcher , D. McClymont and A. Hajimiri 'A fully-integrated quad-band GSM/GPRS CMOS power amplifier', IEEE J. Solid-State Circuits, vol. 43, no. 12, pp.2747 -2758, Dec 2008 [20] G. Liu , P. Haldi , T.-J. K. Liu and A. M. Niknejad 'Fully integrated CMOS power amplifier with efficiency enhancement at power backoff', IEEE J. Solid-State Circuits, vol. 43, no. 3, pp.600 -609, Mar 2008 [21] P. Haldi , D. Chowdhury , P. Reynaert , G. Liu and A. M. Niknejad 'A 5.8 GHz 1 V linear power amplifier using a novel on-chip transformer power combiner in standard 90 nm CMOS', IEEE J. Solid-State Circuits, vol. 43, no. 5, pp.1054 -1063, May 2008 [22] K. H. An , D. H. Lee , O. Lee , H. Kim , J. Han , W. Kim , C.-H. Lee , H. Kim and J. Laskar 'A 2.4 GHz fully integrated linear CMOS power amplifier with discrete power control', IEEE Microw. Wireless Compon. Lett., vol. 19, no. 7, pp.479 -481, July 2009 [23] J. Kim , Y. Yoon , H. Kim , K. H. An , W. Kim , C. -H. Lee and K. T. Kornegay 'A linear multi-mode CMOS power amplifier with discrete resizing and concurrent power combining structure', IEEE J. Solid-State Circuits., vol. 46, no. 5, pp.1034 -1048, May 2011 [24] T. Kuo and B. Lusignan, “A 1.5-W class-F RF power amplifier in0.25-um CMOS technology,” in IEEE Int. Solid-State Circuits Conf.Dig. Tech. Papers, 2001, pp. 154–155. [25] C. Yoo and Q. Huang, “A common-gate switched 0.9-W class-E power amplifier with 41% PAE in 0.25-m CMOS,” IEEE J. Solid-State Circuits, vol. 36, pp. 823–830, May 2001. [26] Johansson and J. Fritzin, “A Review of Watt-Level CMOS RF Power Amplifiers, ”IEEE Transactions on Microwave Theory and Techniques, vol. 62, pp. 111–124, Jan 2014. [27] F. van Rijs 'Status and trends of silicon LDMOS basestation PA technologies to go beyond 2.5 GHz applications', Radio Wireless Symp., pp.69 -72 Jan 2008 [28] R. Sorge , A. Fischer , A. Mai , P. Schley , J. Schmidt , C. Wipf , T. Mausolf , R. Pliquett , R. Barth and K. E. Ehwald 'Complementary RF LDMOS module for 12 V DC/DC converter and 6 GHz power applications', Silicon Monolithic Integr. Circuits in RF Syst., pp.57 -60, Jan 2011 [29] D. Gruner , R. Sorge , O. Bengtsson , A. Al Tanany and G. Boeck 'Analysis, design, and evaluation of LDMOS FETs for RF power applications up to 6 GHz', IEEE Trans. Microw.Theory Techn., vol. 58, no. 12, pp.4022 -4030, Dec 2010 [30] T.Yan, H. Liao, Y. Z. Xiong, R. Zeng, J. Shi, and R. Huang, “Cost-effective integrated RF power transistor in 0.18- m CMOS technology,” IEEE Electron Device Lett., vol. 27, no. 10, pp. 856–858, Oct. 2006. [31] Hao-Shun Yang, Jau-Horng Chen, Yi-Jan Emery Chen, “A 1.2-V 90-nm Fully Integrated Compact CMOS Linear Power Amplifier Using the Coupled L-Shape Concentric Vortical Transformer,” IEEE Trans. Microw. Theory Tech., vol. 62, no. 11, pp. 2689 - 2699, Nov. 2014. [32] A. Afsahi and L. E. Larson, “An integrated 33.5 dBm linear 2.4 GHz power amplifier in 65 nm CMOS for WLAN applications,” in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2010, pp. 1–4. [33] J. Kim et al., “A fully-integrated high-power linear CMOS power amplifier with a parallel-series combining transformer,” IEEE J. Solid-State Circuits, vol. 47, no. 3, pp. 599–614, Mar. 2012. [34] J.-W. Lai and A. Valdes-Garcia, 'A 1V 17.9dBm 60GHz Power Amplifier in Standard 65nm CMOS,' ISSCC Dig. Tech. Papers, pp. 424-425, Feb. 2010. [35] K. Joshin, Y. Kawano, M. Fujita, T. Suzuki, M, Sato, T. Hirose,” A 24 GHz 90-nm CMOS-based power amplifier module with output power of 20 dBm”, IEEE International Symposium on Radio-Frequency Integration Technology, Singapore, Dec. 2009. [36] Y. Kawano, A. Mineyama, T. Suzuki, M. Sato, T. Hirose, and K. Joshin, “A fully-integrated K-band CMOS power amplifier with Psat of 23.8 dBm and PAE of 25.1%,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., Jun. 5–7, 2011, pp. 1–4. [37] Che-Chung Kuo, Yu-Hsuan Lin, Hsin-Chia Lu, Huei Wang” A K-band Compact Fully Integrated Transformer Power Amplifier in 0.18-μm CMOS”, Microwave Conference Proceedings (APMC), 2013 Asia-Pacific, Nov. 2013. [38] Pin-Cheng Huang, ling-Lin Kuo, Zuo-Min Tsai, Kun-You Lin, Huei Wang” A 22-dBm 24-GHz Power Amplifier Using 0.18-um CMOS Technology”, Microwave Symposium Digest (MTT), 2010 IEEE MTT-S International, May 2010. [39] Tao-Yao Chang, Chao-Shiun Wang, and Chorng-Kuang Wang,” A 77 GHz power amplifier using transformer-based power combiner in 90 nm CMOS ”, CICC, Sept. 2010. [40] Doris A. Chan, Milton Feng” A Compact W-Band CMOS Power Amplifier With Gain Boosting and Short-Circuited Stub Matching for High Power and High Efficiency Operation”, Microwave and Wireless Components Letters, Feb 2011 [41] Jau-Jr Lin, Kun-Hin To, Donna Hammock, Bill Knappenberger, Michael Majerus, and W. Margaret Huang, “Power Amplifier for 77-GHz Automotive Radar in 90-nm LP CMOS Technology,” MWCL,May.2010. [42] J. Oh et al., “A 77-GHz CMOS power amplifier with a parallel power combiner based on transmission-line transformer,” IEEE Trans. Microwave Theory and Techniques, vol. 61, pp.2662-2669, July. 2013. [43] K.-Y. Wang, T.-Y. Chang, and C.-K. Wang, “A 1 V 19.3 dBm 79 GHz power amplifier in 65 nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2012, pp. 260–262. [44] Maryam Fathi, David K. Su, Bruce A. Wooley, “A 30.3dBm 1.9GHz-bandwidth 2×4-array stacked 5.3GHz CMOS power amplifier”, Int. Solid-State Circuits Conf. Tech. Dig., Feb 2013. [45] M. Fathi, D. K. Su, and B. A. Wooley, “A stacked 6.5-GHz 29.6-dBm power amplifier in standard 65-nm CMOS,” in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2010, pp. 1–4. [46] P. Haldi, D. Chowdhury, P. Reynaert, G. Liu and A. M. Niknejad “A 5.8 GHz 1 V linear power amplifier using a novel on-chip transformer power combiner in standard 90 nm CMOS”, IEEE J. Solid-State Circuits, vol.43,no.5,pp.1054-1063, May 2008. [47] 曾奕恩撰，應用於無線通訊之瓦等級變壓器功率結合式CMOS功率放大器之研製， 國立台灣大學電信工程所碩士論文，2014 年 7月 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19533 | - |
| dc.description.abstract | 隨著無線通訊系統的發展以及半導體製程的演進，以互補式金氧半場效電晶體實現射頻電路以成本優勢逐漸成為市場焦點，其中功率放大器為收發機中最關鍵的電路之一，本論文將著重於互補式金氧半場效電晶體功率放大器之設計與分析。
論文的第二章描述了一個以90奈米互補式金氧半場效電晶體製程實現一個24-GHz的三個電晶體串接(堆疊式)功率放大器。為了增加單位面積輸出功率以及不犧牲電路可靠度，透過推疊數個電晶體提高供應電壓，並藉由實際模擬來選擇閘級的旁路電容以產生各電晶體適當的負載阻抗，最後透過推挽式的架構，在輸出及輸入端採用變壓器同時達到阻抗匹配、功率結合及單端與差動訊號轉換的功能。晶片面積為0.27 mm2，此電路達到輸出功率21.7dBm。 論文的第三章描述了一個以90奈米互補式金氧半場效電晶體製程實現一個三維結構之77-GHz變壓器功率結合式功率放大器，為了提高輸出功率，以放射狀的功率結合器和功率分配器實現八路功率結合，透過放射狀的功率結合器達到阻抗轉換的功能以降低輸出端匹配網路的阻抗轉換比，藉此降低因高阻抗轉換比造成的損耗，並將放射狀的功率結合器與分配器共用在電路的中央區域的面積，達到三維的結構來縮小因分配器與結合器所佔據的晶片面積，功率放大器的單元採用變壓器以同時達成功率結合、阻抗匹配以及單端與差動訊號的轉換。 論文的第四章描述了以橫向雙擴散金氧半場效電晶體實現一個5-GHz高輸出功率變壓器結合式放大器，透過並聯-並聯結合變壓器(PPCT)的技術，將多組變壓器實現在同一區域，降低在多路功率單元結合時，多個變壓器結合器所需要的面積，因此同時達到面積維持和一路變壓器一樣及多路的功率結合，並使用論文第三段所描述的放射狀三維架構，進一步將晶片面積縮小。 | zh_TW |
| dc.description.abstract | With the development of wireless communication and the evolution of semiconductor process, the radio frequency integrated circuit implemented in CMOS technology become the focal point in the industry with cost advantage. The power amplifier is the most critical component in the transceiver design. Thus the main focus of this thesis is on the design and analysis of power amplifier in CMOS.
The chapter 2 describes a 24 GHz three series-connected (stacked) power amplifier implemented in 90 nm CMOS process. Increasing the supply voltage by stacking FETs to increase the power density per area without sacrificing reliability, and choosing the gate capacitance to generate the proper load impedance of each stacked-transistor by actual simulation. Adopting transformer in input and output terminals to achieve impedance matching, power combining and single to differential ended simultaneously in push-pull topology. The chip size is 0.27 mm2 and output power is 21.7 dBm. The chapter 3 describes a 77 GHz transformer combined power amplifier with 3-D architecture implemented in 90 nm CMOS process. The radial power combiner and splitter achieve the 8-ways power combination to increase output power. The radial power combiner with the function of impedance transformation reduces the impedance transformation ratio of output matching networks and alleviates the loss caused by large impedance transformation ratio. Sharing the center area of the chip to form a 3-D structure and thus the area occupied by the power combiner and power splitter can be reduced. The power cell adopts the transformer to realize power combining, impedance matching and single to differential ended simultaneously. The chapter 4 describes a 5 GHz high output power transformer combined power amplifier implemented in LDMOS process. By parallel-parallel combining transformer technique, the multiple transformers realize in the same area to reduce the area of multiple transformers in multi-way power combination. Thus it can maintain the area as 1-way transformer and function of multi-way power combination simultaneously. And using the 3-D radial architecture described in chapter 3 to further reduce the chip area. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T02:03:58Z (GMT). No. of bitstreams: 1 ntu-105-R02942011-1.pdf: 9658061 bytes, checksum: d2dbc69463939b78da5470a59d436994 (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | 致謝 i
中文摘要 iii ABSTRACT iv CONTENTS vi LIST OF FIGURES ix LIST OF TABLES xiv Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis organization 2 Chapter 2 A compact 24-GHz Stacked-FET CMOS Power Amplifier 3 2.1 Power Combining Techniques 3 2.1.1 Direct Combining 3 2.1.2 Wilkinson Combining 4 2.1.3 Transformer Combining 6 2.2 Circuit Solution for High Supply Voltage 7 2.2.1 Cascode Configuration 7 2.2.2 Stacked Device Structure 7 2.2.3 High-Breakdown Device in CMOS Process 8 2.3 Operation Principle of Power Amplifier Using Stacked-FET structure 8 2.4 Design of 24-GHz CMOS power amplifier using stacked-FET structure 11 2.4.1 Device and Bias Selection 11 2.4.2 Gate Capacitance Selection 13 2.4.3 Output Transformer 18 2.4.4 Input Transformer 27 2.4.5 Transformer-based Stacked-FET Power Amplifier 29 2.5 Simulation Results 31 2.5.1 Small Signal Simulation 31 2.5.2 Large-signal Simulation 33 2.6 Experimental results 33 Chapter 3 A Fully-Integrated 77-GHz CMOS Power Amplifier with Parallel Combining Transformer 38 3.1 Transformer-based Power Combining Techniques 38 3.1.1 Challenges in CMOS Process for High Output Power Amplifier 38 3.1.2 Series-Combining Transformer (Voltage Mode) 39 3.1.3 Parallel-Combining Transformer (Current Mode) 40 3.2 Design of 77-GHz transformer combined power amplifier 41 3.2.1 Common source and Cascode structure 41 3.2.2 Device and Bias Selection 42 3.2.3 Transformer and Power Cell Design 44 3.2.4 Radial Power Splitter and Combiner 52 3.2.5 I/O Matching Network 56 3.2.6 Three–stage 77 GHz Power Amplifier 58 3.3 Simulation Results 60 3.3.1 Small Signal Simulation 60 3.3.2 large-signal simulation 63 3.4 Experimental results 63 Chapter 4 A Fully-Integrated 5-GHz LDMOS Power Amplifier with Parallel- Parallel Combining Transformer and 3-D Architecture 67 4.1 Hybrid Transformer-based Power Combining 67 4.1.1 Parallel-Series and Series-Parallel Combining Transformer 67 4.1.2 Parallel- Parallel Combining Transformer 68 4.2 Design of 5 GHz transformer combined LDMOS power amplifier 70 4.2.1 Device and Bias Selection 70 4.2.2 Transformer and Power Cell Design 75 4.2.3 Parallel-Parallel Combining Network and I/O Matching Network 84 4.2.4 Two–stage 5 GHz Parallel-Parallel Combining Transformer Power Amplifier 85 4.3 Simulation results 87 4.3.1 Small Signal Simulation 87 4.3.2 large-signal simulation 89 Chapter 5 Conclusions 91 REFERENCE 92 | |
| dc.language.iso | en | |
| dc.title | 具三維結構之瓦級並聯-並聯變壓器結合式CMOS功率放大器之研製 | zh_TW |
| dc.title | Research of Watt-Level Parallel-Parallel Transformer Combined CMOS Power Amplifier with 3-D Architecture | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 104-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 蔡政翰(Cheng-Han Tsai),邱煥凱(Hwann-Kaeo Chiou) | |
| dc.subject.keyword | 功率放大器,變壓器結合,電晶體堆疊,高電壓操作, | zh_TW |
| dc.subject.keyword | Power amplifier,Transformer combining,Stacked transistor,High operating voltage, | en |
| dc.relation.page | 95 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2016-03-14 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-105-1.pdf 未授權公開取用 | 9.43 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。