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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19430完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
| dc.contributor.author | Wun-Jian Su | en |
| dc.contributor.author | 蘇文建 | zh_TW |
| dc.date.accessioned | 2021-06-08T01:58:41Z | - |
| dc.date.copyright | 2016-07-04 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-06-28 | |
| dc.identifier.citation | [1]
S. Saxena, R. K. Nandwana, and P. K.Hanumolu, “A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis,” IEEE J. Solid-State Circuits, vol.49, no.8, pp.1827-1836, Aug. 2014. [2] S.-Y. Kao and S.-I. Liu, “A 20-Gb/s Transmitter with Adaptive Pre-Emphasis in 65-nm CMOS Technology,” IEEE Trans. Circuits Syst. II: Expr. Briefs, vol.57, no. 5, pp. 319-323, May 2010. [3] K.-L. J. Wong, H. Hatamkhani, M. Mansuri, and C.-K. K. Yang, “A 27-mW 3.6-Gb/s I/O Transceiver,” IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 602 -612, Apr. 2004. [4] S.-Y. Kao and S.-I. Liu, “A 1.62/2.7 Gbps Adaptive Transmitter with 2-Tap Pre-Emphasis Using a Propagation-Time Detector,” IEEE Trans. Circuits Syst. II: Expr. Briefs, vol.57, no. 3, pp. 178-182, Mar. 2010. [5] J. Lee and H. Wang, “A 20Gb/s Broadband Transmitter with Auto-Configuration Technique,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2007, pp. 444-445. [6] K. Yamaguchi, K. Sunaga, S. Kaeriyama, T. Nedachi, M. Takamiya, K. Nose, Y. Nakagawa, M. Sugawara, and M. Fukaishi, “12-Gb/s Duobinary Signaling with x2 Oversampled Edge Equalization,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2005, pp. 70-71. [7] J. Lee, “A 20-Gb/s Adaptive Equalizer in 0.13-μm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2058-2066, Sep. 2006. [8] S.-Y. Kao and S.-I. Liu, “A 7.5-Gb/s One-Tap-FFE Transmitter with Adaptive Far-End Crosstalk Cancellation Using Duty Cycle Detection,” IEEE J. Solid-State Circuits, vol. 48, no. 2, pp. 391-404, Feb. 2013. [9] J.-R. Schrader, E. A. M. Klumperink, J. Visschers, and B. Nauta, “Pulse-Width Modulation Pre-Emphasis Applied in a Wireline Transmitter, Achieving 33 dB Loss Compensation at 5-Gb/s in 0.13-μm CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 990 -999, Apr. 2006. [10] Y. Lu, K. Jung, Y. Hidaka, and E. Alon, “Design and Analysis of Energy-Efficient Reconfigurable Pre-Emphasis Voltage-Mode Transmitters,” IEEE J. Solid-State Circuits, vol. 48, no. 8, pp. 1898–1909, Aug. 2013. [11] H. Hatamkhani, K.-L. J. Wong, R. Drost, and C.-K. K. Yang, “A 10-mW3.6 Gbps I/O Transmitter,” in IEEE Symp. on VLSI Circuits, June 2003, pp. 97-98. [12] J. Poulton, R. Palmer, A. Fuller, T. Greer, J. Eyles, W. Dally, and M. Horowitz, “A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2745 -2757, Dec. 2007. [13] Y.-H. Song and S. `Palermo, “A 6-Gbit/s Hybrid Voltage-Mode Transmitter with Current-Mode Equalization in 90-nm CMOS,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 8, pp. 491 -495, Aug. 2012. [14] B. Razavi, Design of Integrated Circuits for Optical Communication. New York: McGraw-Hill, 2003. [15] K.-D. Hwang and L.-S. Kim, “A 5 Gbps 1.6 mW/G bps/CH Adaptive Crosstalk Cancellation Scheme with Reference-Less Digital Calibration and Switched Termination Resistors for Single-Ended Parallel Interface,” IEEE Trans. Circuits Syst. I: Regular Papers, vol. 59, no.10, pp. 315-323, Feb. 2014. [16] S. Kim, Y. Jeong, M. Lee, K.-W. Kwon, and J.-H. Chun, “A 5.2-Gb/s Low-Swing Voltage-Mode Transmitter with an AC-/DC-Coupled Equalizer and a Voltage Offset Generator,” IEEE Trans. Circuits Syst. I: Regular Papers, vol. 61, no.1, pp. 213-225, Jan. 2014. [17] S. Shahramian, et. al., “A Pattern-Guided Adaptive Equalizer in 65nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb.2011, pp. 354-355. [18] H. Wang, C.-C. Lee, A.-M. Lee and J. Lee, “A 21-Gb/s 87-mW Transceiver with FFE/DFE/Linear Equalizer in 65-nm CMOS Technology,” in IEEE Symp. on VLSI Circuits, Jun. 2009, pp. 50 -51. [19] J. F. Buckwalter, M. Meghelli, D. J. Friedman, and A. Hajimiri, “Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links,” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1391 -1399, Jun. 2006. [20] K.-L. Jackie Wong, E.-H. Chen and C.-K. Ken Yang, “Edge and Data Adaptive Equalization of Serial-Link Transceivers,” IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 2157-2169, Sep. 2008. [21] T. Anand, A. Elshazly, M. Talegaonkar, B. Young, and P. K. Hanumolu, “A 5 Gb/s, 10 ns Power-On-Time, 36 μW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links,” IEEE J. Solid-State Circuits, vol.49, no.10, pp. 2243-2258, Oct. 2014. [22] G. Ahn, D.-K. Jeong and G. Kim, “A 2-Gbaud 0.7-V Swing Voltage-Mode Driver and On-Chip Terminator for High-Speed NRZ Data Transmission,’’ IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 915-918, Jun. 2000. [23] B. Leibowitz et al., “A 4.3 GB/s Mobile Memory Interface with Power-Efficient Bandwidth Scaling,’’ IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 889-898, Apr. 2010. [24] Y. H. Song, H. W. Yang, H. Li, P. Y. Chiang and S. Palermo, “An 8–16 Gb/s, 0.65–1.05 pJ/b, Voltage-Mode Transmitter with Analog Impedance Modulation Equalization and Sub-3 ns Power-State Transitioning,’’ IEEE J. Solid-State Circuits, vol. 49, no. 11, pp. 2631-2643, Nov. 2014. [25] Y. H. Song, R. Bai, K. Hu, H. W. Yang, P. Y. Chiang and S. Palermo, “A 0.47–0.66 pJ/bit, 4.8–8 Gb/s I/O Transceiver in 65 nm CMOS,’’ IEEE J. Solid-State Circuits, vol. 48, no. 5, pp. 1276-1289, May 2013. [26] Y. H. Seo, Y. S. Kim, H. J. Park and J. Y. Sim, “A 5 Gb/s Transmitter with a TDR-Based Self-Calibration of Preemphasis Strength,' IEEE Trans. Circuits Syst. II: Expr. Briefs, vol. 57, no. 5, pp. 379-383, May 2010. [27] K. S. Kwak, S. K. Hong and O. K. Kwon, “5 Gbit/s 2-Tap Low-Swing Voltage-Mode Transmitter with Least Segmented Voltage-Mode Equalization,” IET Electronics Letters, vol. 50, no. 19, pp. 1371-1373, Sep. 2014. [28] Y. Lu, K. Jung, Y. Hidaka and E. Alon, “A 10Gb/s 10mW 2-Tap Reconfigurable Pre-Emphasis Transmitter in 65nm LP CMOS,” in Proc. IEEE Custom Integr. Circuits Conf., 2012, pp. 1-4. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19430 | - |
| dc.description.abstract | 隨著CMOS製程持續進步，資料傳輸的速度也跟著快速成長。但隨著傳輸速度的提升，許多問題也開始出現，相對於傳輸資料的速度，傳輸通道的有限頻寬就是其中的一個問題，這問題會造成訊號失真與嚴重的符際干擾，在通訊系統中，會將等化器放置於傳送器或是放置於接收器以解決符際干擾問題。因為傳輸通道的材質和長度會隨著應用而有所不同，因此等化器會搭配一個可適性的演算法，使電路可工作在不同的通道。
本論文提出一個使用時間模式去加強法的可適性電壓模式傳送器。此時間模式去加強法是使用功率平衡法來決定責任週期，並利用脈波寬度調變來控制所需的補償增益。我們提出的可適性演算法不需要額外的輔助傳輸線，並且可以忍受製程變異。此電路實現於40奈米製程，其傳送器和接收器的面積各為0.075mm2和0.105mm2。在每秒50億位元的傳輸速率下，此傳送器能操作在通道損耗為15 dB的環境，且量測到的方均根抖動為12.25 ps，其位元錯誤率小於10-12。此電路的校正時間為2.048 us。在1.1伏特電壓操作下，此傳送器功率消耗9.3mW，而接收發器整體的功率消耗為17.5mW。 | zh_TW |
| dc.description.abstract | With the CMOS technology continues to progress, the data rate is also fast growing in different applications. As data rate keeps rising, many significant problems appear. One of the problem is that the channel bandwidth limits compared with the data rate. It will result in a significant inter symbol interference (ISI) and cause signal distortion. In communication systems, equalizers are widely adopted in transmitter side or receiver side to deal with ISI. The length or the material of the transmission channel may be different for various applications. Therefore, an equalizer with the adaptive algorithm is widely adopted in communication systems.
A 5-Gb/s adaptive voltage-mode (VM) transmitter using time-based de-emphasis is presented. The duty cycle of the pulse width modulation is adjusted by the spectrum-balancing technique. For different cable lengths, the duty cycle of the PWM data is adaptively adjusted. The proposed adaptive VM transmitter does not require any auxiliary channels. The proposed adaptive VM transmitter can tolerate the process variations. This adaptive transmitter is fabricated in a 40-nm CMOS process. The active areas of the transmitter and the receiver are 0.075mm2 and 0.105mm2, respectively. For a 5-Gb/s PRBS of 27-1 passing through a 9-m coaxial cable with a 15.35-dB loss, the measured root-mean-square jitters of the recovered data is 12.25 ps. The measured bit error rate is less than 10-12. The settling time for adaptive time-based de-emphasis is 2.048us. For a 1.1V supply voltage, the power of the transmitter is 9.3mW and the total power of the transceiver is 17.5mW. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T01:58:41Z (GMT). No. of bitstreams: 1 ntu-105-R01943015-1.pdf: 4212480 bytes, checksum: e8ae32f5839cfcf8938717df7553122f (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | 1. Introduction……………………………………………………….….1
1.1 Overview……………...…………….………………………………. 2 1.2 Wireline Communication...…………………………………………. 2 1.3 Conventional Transmitter Signaling…………….…………...............3 1.3.1 Current Mode Driver…….…………………….…………………..4 1.3.2 Voltage Mode Driver…….…………..…………….........................5 2. Analysis of the Time-Based De-Emphasis…………………………….6 2.1 Time-Based De-Emphasis……………………………………………7 2.1.1 Signaling Description…….…………..…………….........................7 2.1.2 Analysis in Frequency Domain….……….….…………………..…7 2.1.3 Analysis in Time Domain….……….……………………………....9 3. A 5Gb/s Voltage-Mode Transmitter Using Adaptive Time-Based De-Emphasis………………………………………………………………..20 3.1 Motivation………………………………………….…………….…21 3.2 Circuit Architecture...……………..………………….……………..23 3.2.1 Algorithm Description…………………..……..….………………23 3.3 Circuit Description………………………………………….............28 3.3.1 Pulse-Width Modulation Encoder…………..……………….…....28 3.3.2 Single-ended Driver and Differential Driver……………….….….33 3.3.3 Transmitter Controller………...…………..…………...……….…37 3.3.4 Calibration Circuit………………………………….…..….……...40 3.3.5 Receiver Controller…………………….……...……………….…43 3.3.6 Analysis……………………………………………………….…..45 3.4 Measurement Setup and Experimental Results…….……..….……..46 3.4.1 Measurement Setup…………..……………..………………....….46 3.4.2 Experimental Results……………………………………………..47 3.4.3 Die Photo and Performance Summary...………….………………53 4. Conclusion and Future Work………………………………………....56 4.1 Conclusion………………………………………………………..…57 4.2 Future Work…………………………………………………………57 Bibliography……………………………………………………….……58 | |
| dc.language.iso | en | |
| dc.title | 使用時間模式去加強法之50億位元可適性電壓模式傳送器 | zh_TW |
| dc.title | A 5 Gb/s Voltage-Mode Transmitter Using Adaptive Time-Based De-Emphasis | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 104-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),陳巍仁(Wei-Zen Chen),陳奕宏(E-Hung Chen) | |
| dc.subject.keyword | 電壓模式傳送器,脈波寬度調變,符際干擾,可適性去加強法, | zh_TW |
| dc.subject.keyword | Voltage-mode transmitter,pulse-width modulation,inter-symbol interference,adaptive de-emphasis, | en |
| dc.relation.page | 61 | |
| dc.identifier.doi | 10.6342/NTU201600534 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2016-06-29 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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