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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 吳肇欣(Chao-Hsin Wu) | |
dc.contributor.author | Chia-Ming Chang | en |
dc.contributor.author | 張家銘 | zh_TW |
dc.date.accessioned | 2021-06-08T01:48:56Z | - |
dc.date.copyright | 2016-08-03 | |
dc.date.issued | 2016 | |
dc.date.submitted | 2016-08-01 | |
dc.identifier.citation | [1] M. Bohr, “The Evolution of Scaling from the Homogeneous era to the Heterogeneous era”, in IEEE International Electron Devices Meeting (IEDM) , 2011, pp. 1-6.
[2] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B.McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson and M. Bohr, “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors”, in IEEE International Electron Devices Meeting (IEDM), 2003, pp. 978-981. [3] R. Granzner, S. Thiele, C. Schippel, and F. Schwierz,” Quantum Effects on the Gate Capacitance of Trigate SOI MOSFETs” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 57, no. 12, pp.3231-3238, Dec. 2010. [4] H.-H. Shen, S.-L. Shen, C.-H. Yu, and P. Su, “Impact of Quantum Capacitance on Intrinsic Inversion Capacitance Characteristics and Inversion-Charge Loss for Multi-gate III–V-on-Insulator nMOSFETs”, IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 63, no. 1, pp. 339-344, Jan. 2016. [5] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C.-H. Choi,G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He#, J. Hicks , R. Huessner, D. Ingerly,P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz#, B. McIntyre, P. Moon, J. Neirynck, S. Pae,C. Parker, D. Parsons, C. Prasad#, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren°, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, K. Zawadzki “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging”, in IEEE International Electron Devices Meeting (IEDM), 2007, pp. 247-250. [6] Retrieved July 5, 2016, from http://www.ioffe.ru/SVA/NSM/Semicond/ [7] T. Mimula, “The Early History of the High Electron Mobility Transistor(HEMT)”, in IEEE Transactions on Microwave Theory and Techniques, vol. 50, no. 3, pp. 780-782 ,Mar. 2002. [8] J. A. del Alamo, D. Antoniadis, A. Guo1, D.-H. Kim, T.-W. Kim, J. Lin, W. Lu1, A. Vardi, and X. Zhao, “InGaAs MOSFETs for CMOS: Recent Advances in Process Technology”, in IEEE International Electron Devices Meeting (IEDM), 2013, pp. 24-27. [9] Peide D. Ye, Fundamentals of III-V Semiconductors MOSFETs, Springer New York, Jun. 2010. [10] É. O’Connor, B. Brennan, V. Djara, K. Cherkaoui, S. Monaghan, S. B. Newcomb, R. Contreras, M. Milojevic, G.Hughes, M. E. Pemble, R. M. Wallace, and P. K. Hurley, “A systematic study of (NH4)2S passivation (22%, 10%, 5%, or 1%) on the interface properties of the Al2O3/In0.53Ga0.47As/InP system for n-type and p-type In0.53Ga0.47As epitaxial layers”, J. Appl. Phys., vol. 109, no.024101, pp.1-10, 2011. [11] J. Valasek, “PIEZOELECTRIC AND ALLIED PHENOMENA IN ROCHELLE SALT”, American Physical Society, vol. XV, no.6, pp.537-538., 1920. [12] Youn Jung Park, In-sung Bae, Seok Ju Kang, Jiyoun Chang and Cheolmin Park, “Control of Thin Ferroelectric Polymer Films for Non-volatile Memory Applications”, IEEE Transactions on Dielectrics and Electrical Insulation, vol. 17, no. 4, Aug. 2010. [13] Kwang-Ho Kim, Jin-Ping Han,Soon-Won Jung, and Tso-Ping Ma, “Ferroelectric DRAM (FEDRAM) FET With Metal/SrBi¬Ta¬O9/SiN/Si Gate Structure”, IEEE ELECTRON DEVICE LETTERS, vol. 23, no. 2, Feb. 2002. [14] Shao Song Fu, Hao Yu, Xiao Ya Luo, Yu Long Jiang, and Guo Dong Zhu, “The Influence of Ultraviolet Irradiation on Polarization Fatigue in Ferroelectric Polymer Films”, IEEE ELECTRON DEVICE LETTERS, vol. 33, no. 1, Jan. 2012. [15] D. E. Fisch, N. E. Abt, F. N. Bens, W. D. Miller, T. Pramanik, W. Saiki, W.H. Shepherd, “Analysis of Thin Film Ferroelectric Aging”, IEEE, 28th Annual Proceedings on Reliability Physics Symposium, New Orleans, LA, USA, 27-29 Mar. 1990, pp. 237-242. [16] Karin M. Rabe, Charles H. Ahn, and Jen-Marc Triscone, Physics of Ferroelectrics, Springer Berlin Heidelberg, Jun. 2007. [17] S. Salahuddin and S. Datta, “Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices”, Nano Letters, vol. 8, no.2, pp. 405-410, 2008. [18] S. Salahuddin and S. Datta, “Can the subthreshold swing in a classical FET be lowered below 60mV/decade?”, in IEEE International Electron Devices Meeting (IEDM), 2008, pp. 693-696. [19] J. Tao, C. Z. Zhao, P. Taechakumput, M. Werner, S. Taulor, and P. R. Chalker, “Extrinsic and Intrinsic Frequency Dispersion of High-k Materials in Capacitance-Voltage Measurements”, Materials, vol.5, no.6, pp.1005-1032, 2012. [20] L. M. Terman, “An Investigation of Surface States at Silicon/Silicon Oxide Interface Employing Metal-Oxide-Silicon Diodes”, Solid-State Electronics, vol. 5, pp. 285-299, 1962. [21] A. Pacelli, A. L. Lacaita, S. Villa, and L. Perron, “Reliable Extraction of MOS Interface Traps from Low-Frequency CV Measurements”, IEEE ELECTRON DEVICE LETTERS, vol. 19, no. 5, May 1998. [22] R. Castagne, and A. Vapaille, “Apparent Interface State Density Introduced by the Spatial Fluctuations of Surface Potential in an M.O.S. Structure”, IEEE ELECTRONICS LETTERS , vol. 6, no. 22, pp.691-694, Oct. 1970. [23] E. H. Nicollian and A. Goetzberger, “MOS Conductance Technique for Measuring Surface State Parameters”, Appl. Phys. Lett., vol.7, no.8, pp.216-219, 1965. [24] International Technology Roadmap for Semiconductor(IRTS) [25] Adrian M. Ionescu, Luca De Michielis, Nilay Dagtekin, Giovanni Salvatore, Ji Cao, Alexandru Rusu, and Sebastian Bartsch, “Ultra low power: emerging devices and their benefits for Integrated Circuits”, in IEEE International Electron Devices Meeting (IEDM), 2011, pp. 378-381. [26] M. H. Lee, P.-G. Chen, C. Liu, K-Y. Chu, C.-C. Cheng, M.-J. Xie, S.-N. Liu, J.-W. Lee, S.-J. Huang, M.-H. Liao, M. Tang, K.-S. Li and M.-C. Chen, “Prospects for Ferroelectric HfZrOx FETs with Experimentally CET=0.98nm, SSfor=42mV/dec, SSrev=28mV/dec, Switch-OFF<0.2V, and Hysteresis-Free Strategies”, in IEEE International Electron Devices Meeting (IEDM), 2015, pp.616-619. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19209 | - |
dc.description.abstract | 引入半導體產業最重要的摩爾定律做為引子後,簡述半導體製造在各節點技術演進上,碰上對應的製程技術挑戰與如何克服之過程,以及藉由現今研究之趨勢,對未來10奈米以下節點技術發展做預測,同時簡單介紹何為短通道及窄通道效應。
本論文第一部分簡述三五族材料特性、高載子遷移率電晶體之發展歷史與現況,並提出鰭狀結構之高載子遷移率電晶體,透過TCAD進行模擬,並由模擬結果建立其閘極控制機制之理論,同時透過製程實作出元件並進行量測分析,可成功的以該理論解釋量測分析之結果。 第二部分簡述鐵電材料之材料特性,並以電路學與能量兩個不同角度切入解釋負電容之成因,透過製程實作出電容元件,並進行量測與分析,探討鐵電材料於不同結晶溫度下,在不同頻率下的電容電壓特性及漏電流特性,同時以電導法分析其介面特性,探討不同退火溫度對介面特性之影響。 第三部分簡述鐵電材料應用於電晶體之發展與其優缺點,以製程實作出元件,同時進行量測與分析,探討不同退火溫度對元件特性造成之影響,並以TCAD模擬,探討不同模擬條件下之元件特性,作為未來的改進方向。 | zh_TW |
dc.description.abstract | After describing Moore’s Law, we introduce node technology progression of semiconductor manufacturing in this thesis, including the corresponding challenges and the solution to them. After studying research trends, we predict sub-10nm node technology development, and introduce short-channel effects (SCEs) and narrow-channel effects (NCEs) briefly.
In the first part, we introduce III-V material characteristics, and their developing history and operating principles of high electron mobility transistors (HEMTs). We propose fin structures of HEMTs, and use TCAD to simulate. From simulation results, the theory of gate control mechanisms is proposed. We fabricate and measure the device, the measurement results can be explained by the proposed theory successfully. In the second part, we introduce ferroelectric material to form negative capacitance (NC), and use two different viewpoints of circuit and energy to explain it. We fabricate MOS capacitances and discuss their C-V, I-V, and interface characteristics at different crystalline temperatures and frequencies. In the third part, we introduce development, pros and cons of negative capacitance field effect transistors (NCFETs). We fabricate and discuss their I-V characteristics in different crystalline temperatures. Finally, we use TCAD to simulate different conditions of NCHEMTs, and the results are regarded as improving ways in the future. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T01:48:56Z (GMT). No. of bitstreams: 1 ntu-105-R03941005-1.pdf: 6067886 bytes, checksum: 00e63819f817886c414d7d94ef0290c7 (MD5) Previous issue date: 2016 | en |
dc.description.tableofcontents | 口試委員審定書 i
誌謝 ii 中文摘要 v ABSTRACT vi 目錄 viii 圖目錄 x 表目錄 xiv 第1章 緒論 1 1.1 背景介紹 1 1.1.1 摩爾定律 1 1.1.2 製程技術挑戰與未來發展 3 1.1.3 短通道效應及窄通道效應 6 1.2 論文概述 10 第2章 鰭狀砷化銦鎵高載子遷移率電晶體之製作與電特性分析 11 2.1 背景介紹 11 2.1.1 三五族材料簡介 11 2.1.2 高載子遷移率電晶體之簡介 14 2.1.3 高載子遷移率電晶體之發展現況 16 2.2 鰭狀砷化銦鎵高載子遷移率電晶體之製作流程 18 2.3 鰭狀砷化銦鎵高載子遷移率電晶體之閘極控制原理簡介 23 2.4 鰭狀砷化銦鎵高載子遷移率電晶體之電特性分析 27 2.4.1 電流電壓特性分析 27 2.4.2 電子遷移率之萃取與簡易散射模型分析 33 2.5 本章結論與未來研究方向 43 第3章 氧化鉿鋯沉積於n型砷化鎵基板之金氧半電容元件製作與電容分析 44 3.1 背景介紹 44 3.1.1鐵電材料簡介 44 3.1.2 鐵電材料負電容特性簡介 48 3.2 元件製作流程 54 3.3 電容特性分析 56 3.3.1 電容電壓與電流電壓特性分析 56 3.1.2 電容介面特性分析 60 3.4 本章結論與未來發展 66 第4章 氧化鉿鋯應用於鰭狀砷化銦鎵高載子遷移率電晶體之電特性分析 67 4.1 背景介紹 67 4.1.1 為何需要陡峭的次臨界擺幅? 67 4.1.2 陡峭次臨界擺幅元件介紹 70 4.1.3 基板因數(body factor) 72 4.2 製作流程 74 4.3 電流特性分析 78 4.3.1 電流電壓特性分析 78 4.3.2 負電容產生條件 81 4.3.3 以TCAD模擬負電容高載子遷移率電晶體之電流電壓特性 83 4.4 本章結論與未來發展 89 第5章 結論 90 參考文獻 92 | |
dc.language.iso | zh-TW | |
dc.title | 鰭狀砷化銦鎵高載子遷移率電晶體之研究 | zh_TW |
dc.title | Investigation of the InGaAs Fin Structure High Electron Mobility Transistors | en |
dc.type | Thesis | |
dc.date.schoolyear | 104-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 林浩雄(Hao-Hsiung Lin),黃建璋(Jian-Jang Huang),吳育任(Yuh-Renn Wu),陳敏璋(Min-Jang Chen) | |
dc.subject.keyword | 鰭狀砷化銦鎵高載子遷移率電晶體,鰭狀場效電晶體,TCAD,負電容電晶體,負電容高載子遷移率電晶體,鐵電材料, | zh_TW |
dc.subject.keyword | InGaAs FinHEMT,FinFET,TCAD,NCFET,NCHEMT,Ferroelectric material, | en |
dc.relation.page | 95 | |
dc.identifier.doi | 10.6342/NTU201601720 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2016-08-01 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 光電工程學研究所 | zh_TW |
顯示於系所單位: | 光電工程學研究所 |
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