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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 郭大維(Tei-Wei Kuo) | |
| dc.contributor.author | Tse-Yuan Wang | en |
| dc.contributor.author | 王澤元 | zh_TW |
| dc.date.accessioned | 2021-06-08T01:47:22Z | - |
| dc.date.copyright | 2016-08-24 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-08-05 | |
| dc.identifier.citation | [1] Quality of service (qos) - samsung, 2014.
[2] Amir Ban. Flash File System. US Patent 5,404,485. In M-Systems, April 1995. [3] M.-L. Chiang and R.-C. Chang. Cleaning policies in mobile computers using flash memory. J. Syst. Softw., 48(3):213–231, November 1999. [4] Aayush Gupta, Youngjae Kim, and Bhuvan Urgaonkar. DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings. In ASPLOS, 2009. [5] Longzhe Han, Yeonseung Ryu, and Keunsoo Yim. Cata: A garbage collection scheme for flash memory file systems. In Jianhua Ma, Hai Jin, LaurenceT. Yang, and JeffreyJ.-P. Tsai, editors, Ubiquitous Intelligence and Computing, volume 4159 of Lecture Notes in Computer Science, pages 103–112. Springer Berlin Heidelberg, 2006. [6] Myoungsoo Jung, Wonil Choi, Shekhar Srikantaiah, Joonhyuk Yoo, and Mahmut T.Kandemir. Hios: A host interface i/o scheduler for solid state disks. SIGARCH Comput. Archit. News, 42(3):289–300, June 2014. [7] Myoungsoo Jung, Ellis H Wilson III, and Mahmut Kandemir. Physically addressed queueing (paq): improving parallelism in solid state disks. In ACM SIGARCH Computer Architecture News, volume 40, pages 404–415. IEEE Computer Society, 2012. [8] Atsuo Kawaguchi, Shingo Nishioka, and Hiroshi Motoda. A flash-memory based file system. In Proceedings of the USENIX 1995 Technical Conference Proceedings, TCON’95, pages 13–13, Berkeley, CA, USA, 1995. USENIX Association. [9] Jesung Kim, Jong Min Kim, S.H. Noh, Sang Lyul Min, and Yookun Cho. A space efficient flash translation layer for compactflash systems. Consumer Electronics, IEEE Transactions on, 48(2):366–375, May 2002. [10] S.-W. Lee, D.-J. Park, T.-S. Chung, D.-H. Lee, S. Park, and H.-J. Song. A log buffer-based flash translation layer using fully-associative sector translation. ACM Transactions on Embedded Computing Systems, July 2007. [11] Bo Mao and Suzhen Wu. Exploiting request characteristics and internal parallelism to improve ssd performance. In Computer Design (ICCD), 2015 33rd IEEE Inter- national Conference on, pages 447–450. IEEE, 2015. [12] Y. Wang, Z. Qin, R. Chen, Z. Shao, Q. Wang, S. Li, and L. T. Yang. A real-time flash translation layer for nand flash memory storage systems. IEEE Transactions on Multi-Scale Computing Systems, 2(1):17–29, Jan 2016. [13] Qi Zhang, Xuandong Li, Linzhang Wang, Tian Zhang, Yi Wang, and Zili Shao. Lazy-rtgc: A real-time lazy garbage collection mechanism with jointly optimizing average and worst performance for nand flash memory storage systems. ACM Transactions on Design Automation of Electronic Systems (TODAES), 20(3):43, 2015. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19168 | - |
| dc.description.abstract | 快閃記憶體的市場趨向顯示有越來越多的雲端儲存系統採用快閃記憶體當作儲存裝置，基於快閃記憶體的雲端儲存系統面臨必須滿足服務品質的挑戰，例如提供可預測的回應時間。然而，由於快閃記憶體的特性，當快閃記憶體儲存裝置觸發垃圾回收指令時，可能導致上層指令無法被立即的服務，這個現象導致不可預期的效能下降，產生回應時間差異過大的問題，因此如何最小化反應時間的差異性對基於快閃記憶體的雲端儲存系統是相當重要的議題，基於上述觀察，為了解決反應時間的差異性過大的問題，我們提出一個以配對為導向來減少快閃記憶體儲存裝置反應時間之最長的設計，最後，藉由實驗結果，我們驗證了所提出方法能有效減少快閃記憶體儲存裝置的最大反應時間。 | zh_TW |
| dc.description.abstract | The market trend of flash memory shows that more and more flash storage devices are widely used in cloud storage systems. Flash-based storage servers face the challenge on fulfilling the requirement of quality of service (QoS); for example, offering predictable response time. However, due to the characteristics of flash memory, host commands are unable to process promptly when garbage collection is triggered. This phenomenon leads to unexpected performance degradation. Therefore, the critical issue for flash-based storage servers is to minimize the response-time variation. Based on the above observations, in order to resolve response-time variation problem, we propose a partnership design to minimize the maximal response time. Experimental results show that the proposed design is very effective in reducing the maximal response time of flash-memory storage devices. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T01:47:22Z (GMT). No. of bitstreams: 1 ntu-105-R03922064-1.pdf: 568185 bytes, checksum: d736cec1a670ede0def625cec00753c1 (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | Contents
Abstract in Chinese iv Abstract v Contents vii List of Figures ix List of Tables x 1 Introduction 1 2 Background and Research Motivation 4 3 A Partnership-Based Approach Design 8 3.0.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.0.2 APartnership-BasedApproachDesign . . . . . . . . . . . . . . 10 3.0.3 GarbageCollection . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 PERFORMANCE EVALUATION 14 4.0.4 EvaluationMetricsandExperimentSetup . . . . . . . . . . . . . 14 4.0.5 ExperimentResults . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Conclusion 16 Bibliography 17 | |
| dc.language.iso | en | |
| dc.title | 以配對為導向來減少快閃記憶體儲存裝置之最長反應時間 | zh_TW |
| dc.title | A Partnership-Based Approach to Minimize the Maximal Response-Time of Flash-Memory Storage Devices | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 104-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.coadvisor | 張原豪(Yuan-Hao Chang) | |
| dc.contributor.oralexamcommittee | 楊佳玲(Chia-Lin Yang),賴尚宏(Shang-Hong Lai),曾煜棋(Yu-Chee Tseng) | |
| dc.subject.keyword | 儲存系統,快閃記憶體,效能,垃圾回收,配對, | zh_TW |
| dc.subject.keyword | Storage system,Flash memory,Performance,Garbage collection,Partnership, | en |
| dc.relation.page | 17 | |
| dc.identifier.doi | 10.6342/NTU201600812 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2016-08-07 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
| 顯示於系所單位： | 資訊工程學系 | |
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