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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18982完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成(Tai-Cheng Lee) | |
| dc.contributor.author | Chun-Ping Wang | en |
| dc.contributor.author | 王俊彬 | zh_TW |
| dc.date.accessioned | 2021-06-08T01:41:28Z | - |
| dc.date.copyright | 2016-08-25 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-08-18 | |
| dc.identifier.citation | [1] E. Temporiti, G. Albasini, I. Bietti, R. Castello, and M. Colombo, “A 700-kHz bandwidth Σ-∆ fractional synthesizer with spurs compensation and linearization
techniques for WCDMA applications,” IEEE J. Solid-State Circuits, vol.39, no.9, pp.1446-1454, Sep. 2004. [2] S. E. Meninger, and M. H. Perrott, “A fractional-N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantizationinduced phase noise,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process, vol. 50, no. 11, pp.839-849, Nov. 2003. [3] S. Pamarti, L. Jansson, and I. Galton, “A wideband 2.4-GHz delta-sigma fractional-N PLL with 1-Mb/s in–loop modulation,” IEEE J. Solid-State Circuits, vol.39, no.1, pp.49-62, Jan. 2004. [4] H. M. Chien, et. al., “A 4GHz fractional-N synthesizer for IEEE 802.11a,” IEEE VLSI, pp. 46-49, Jun. 2004. [5] S. E. Meninger and M. H. Perrott, “A 1-MHz Bandwidth 3.6-GHz 0.18-µm CMOS Fractional-N Synthesizer Utilizing a Hybrid PFD/DAC Structure for Reduced Broadband Phase Noise,” IEEE J. Solid-State Circuits , vol. 41, no. 4, pp. 966-980, Apr. 2006. [6] H. Hedayati, B. Bakkaloglu and W. Khalil, “Closed loop nonlinear modeling of wideband Σ∆ fractional-N frequency synthesizers,“ IEEE Trans. on Microwave Theory and Techniques, vol. 54, no. 10, pp. 3654-3663, Oct. 2006. [7] W. Khalil, H. Hedayati, B. Bakkaloglu and S. Kiaei, “(Invited) analysis and modeling of noise folding and spurious emission in wideband fractional-N synthesizers,” IEEE Radio Frequency Integrated Circuits Symposium, pp. 291-294, 2008. [8] H. Arora et. al., “Enhanced phase noise modeling of fractional-N frequency synthesizers,” IEEE Trans. on Circuits and Systems-I: Regular Papers, vol. 52, no. 2, pp. 379-395, Feb. 2005. [9] C. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli, and Z. Wang, “A family of low-power truly modular programmable dividers in standard 0.35-um CMOS technology,” IEEE J. Solid-State Circuits, vol. 35, no. 7, pp. 1039-1045, July 2000. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18982 | - |
| dc.description.abstract | 本論文提出一個用於降低小數型頻率合成器中近頻雜訊的架構。此架構藉由雙頻信號產生器改變鎖相迴路中參考信號的頻率，可以控制相位頻率偵測器/電流幫浦操作在遠離非線性區。如此，可提高相位頻率偵測器/電流幫浦操作時之線性度，進而降低近頻雜訊。藉由相關參數的調整，此架構可以操作在一個具有最佳相位雜訊表現的最佳操作點。
這個架構以零點一八微米互補式金氧半製程，在 1.17 x 1.20 平方毫米的面積上實現。完整的電路包含了一個操作於 700MHz~1300MHz 的三角積分調變式小數型頻率合成器及雙頻信號產生器。實驗結果顯示，在1.8 伏特的電源供應下，耗電量為 23.5mA。當頻率在~800MHz 時，在 10 kHz 到 10 MHz 的積分範圍內，其方均根抖動值可以由 26.45 ps 降低至 3.91 ps。 | zh_TW |
| dc.description.abstract | A fractional-N PLL employing a dual-frequency clock generator is proposed to achieve lowering the in-band phase noise. The architecture enables the PFD/CP to operate in the linear region to avoid noise-folding effect. An optimum operating condition can be tuned to achieve the best in-band phase noise. The proposed techniques are employed in a 700~1300 MHz fractional-N PLL fabricated in a 0.18-μm CMOS process with a 1.17 mm x 1.20 mm die area. The experimental results demonstrate that the integrated rms jitter (10 kHz to 10 MHz) in the fractional-N PLL can be greatly improved from 26.45 ps to 3.91 ps when frequency is ~800MHz. This fully-integrated PLL dissipates 23.5 mA from a 1.8-V supply. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T01:41:28Z (GMT). No. of bitstreams: 1 ntu-105-P99943001-1.pdf: 2031537 bytes, checksum: 9a09b940c5ce85ae2fe89cf89e982788 (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | 摘要 i
Abstract ii Contents iii List of Figures v List of Tables vii Chapter 1 Introduction 8 1.1 Motivation and Research Goals 8 1.2 Thesis Organization 8 Chapter 2 Proposed Fractional-N Frequency Synthesizer 10 2.1 Block Diagram 10 2.2 Dual-Frequency Clock Generator 11 2.3 Summary 12 Chapter 3 Analysis of the Proposed Architecture 13 3.1 Operating Far from Nonlinear-Zone in PFD/CP 13 3.1.1 Operation 13 3.1.2 Reduction of Noise 15 3.2 Induced Noises and Spurs 16 3.2.1 Thermal and Flicker Noise from Charge Pump 16 3.2.2 Fractional Spurs 16 3.2.2.1 fspur is larger than loop bandwidth 17 3.2.2.2 fspur is smaller than loop bandwidth 18 3.3 Optimum Operating Point 18 Chapter 4 Simulation 19 4.1 Pure Behavior Simulation 19 4.1.1 Linear Model Simulation 19 4.1.2 Non-linear PFD/CP Model Simulation 20 4.2 Behavior Simulation with PFD/CP in Transistor-Level 21 4.3 Verification of Thermal Noise Contribution 22 Chapter 5 Circuit Implementation 24 5.1 Dual-Freauency Clock Geenrator 24 5.1.1 Unit Cell of Delay 26 5.2 PFD/CP 26 5.3 VCO 27 5.4 Divider 28 5.5 VCO Output Buffer for Measurement 30 Chapter 6 Experimental Results 31 6.1 Measurement Environment 31 6.2 Die Area and Power Dissipation 33 6.3 VCO Gain 34 6.2 Phase Noise and RMS Jitter 36 Chapter 7 Conclusion 39 7.1 Thesis Summary 39 7.2 Future Works 39 Bibliography 40 About the Author 42 | |
| dc.language.iso | en | |
| dc.subject | 非線性 | zh_TW |
| dc.subject | 小數型頻率合成器 | zh_TW |
| dc.subject | 近頻雜訊 | zh_TW |
| dc.subject | 時間延遲 | zh_TW |
| dc.subject | 雙頻信號產生器 | zh_TW |
| dc.subject | 雜訊摺疊 | zh_TW |
| dc.subject | dual-frequency reference clock | en |
| dc.subject | noise folding | en |
| dc.subject | Fractional-N PLL | en |
| dc.subject | in-band phase noise | en |
| dc.subject | time delay | en |
| dc.subject | non-linearity | en |
| dc.title | 一種降低小數型頻率合成器近頻雜訊的技術 | zh_TW |
| dc.title | A Technique of In-Band Phase Noise Reduction in
Fractional-N Frequency Synthesizers | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 104-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉深淵,郭泰豪,黃柏鈞 | |
| dc.subject.keyword | 小數型頻率合成器,近頻雜訊,時間延遲,雙頻信號產生器,非線性,雜訊摺疊, | zh_TW |
| dc.subject.keyword | Fractional-N PLL,in-band phase noise,time delay,dual-frequency reference clock,non-linearity,noise folding, | en |
| dc.relation.page | 42 | |
| dc.identifier.doi | 10.6342/NTU201603046 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2016-08-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
| ntu-105-1.pdf 未授權公開取用 | 1.98 MB | Adobe PDF |
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