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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李建模(Chien-Mo Li) | |
| dc.contributor.author | Shih-Yao Lin | en |
| dc.contributor.author | 林士堯 | zh_TW |
| dc.date.accessioned | 2021-06-08T01:37:55Z | - |
| dc.date.copyright | 2017-02-08 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-12-08 | |
| dc.identifier.citation | [1] Ahmed, Nisar, Mohammad Tehranipoor, and Vinay Jayaram. 'Transition delay fault test pattern generation considering supply voltage noise in a SOC design.' Proceedings of the 44th annual Design Automation Conference. ACM, 2007, pp. 533-538.
[2] ANSYS RedHawk. Available: https://www.apache-da.com/products/redhawk [3] Apache RedHawk User Manual, 2015. [4] Bastani, Pouria, et al. 'Speedpath prediction based on learning from a small set of examples.' Proceedings of the 45th annual Design Automation Conference. ACM, 2008, pp. 217 - 222. [5] Christopher M. Bishop, Pattern Recognition and Machine Learning: Springer, 2007. [6] Chen, Howard H., and David D. Ling. 'Power supply noise analysis methodology for deep-submicron VLSI chip design.' Proc. Design Automation Conference. ACM, 1997, pp. 638-648. [7] Chen, Howard H., and J. Scott Neely. 'Interconnect and circuit modeling techniques for full-chip power supply noise analysis.' IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B 21.3 (1998): 209-215. [8] Daasch, W. Robert, and Robert Madge. 'Data-driven models for statistical testing: measurements, estimates and residuals.' IEEE International Conference on Test, 2005.. IEEE, 2005. p. 10 pp. -322. [9] Duda, Richard O., Peter E. Hart, and David G. Stork. Pattern classification. John Wiley & Sons, 2012. [10] Fast Artificial Neural Network. Available: http://libfann.github.io/fann/docs/files/fann-h.html [11] Firouzi, Farshad, et al. 'Representative critical-path selection for aging-induced delay monitoring.' 2013 IEEE International Test Conference (ITC). IEEE, 2013, pp. 1-10. [12] Firouzi, Farshad, et al. 'Aging-and variation-aware delay monitoring using representative critical path selection.' ACM Transactions on Design Automation of Electronic Systems (TODAES) 20.3 (2015): 39. [13] Girard, Patrick, Nicola Nicolici, and Xiaoqing Wen, eds. Power-aware testing and test strategies for low power devices. Springer Science & Business Media, 2010. [14] C.-Y. Han, Y.-C. Li, H.-T. Kan, and James C.-M. Li, “Power-Supply-Noise-Aware Test Pattern Analysis and Regeneration for Yield Improvement,” IEICE, Vol.E99-A, No.12, pp.-,Dec. 2016. [15] Jiang, Yi-Min, and Kwang-Ting Cheng. 'Analysis of performance impact caused by power supply noise in deep submicron devices.' Proceedings of the 36th annual ACM/IEEE Design Automation Conference. ACM, 1999, pp. 760-765. [16] Kahng, Andrew B., Mulong Luo, and Siddhartha Nath. 'SI for free: machine learning of interconnect coupling delay and transition effects.' System Level Interconnect Prediction (SLIP), 2015 ACM/IEEE International Workshop on. IEEE, 2015, pp. 1-8 [17] Lee, Kuen-Jong, Tsung-Chu Haung, and Jih-Jeen Chen. 'Peak-power reduction for multiple-scan circuits during test application.' Test Symposium, 2000.(ATS 2000). Proceedings of the Ninth Asian. IEEE, 2000, pp.453-458. [18] Lee, Jeremy, et al. 'Layout-aware, IR-drop tolerant transition fault pattern generation.' Proceedings of the conference on Design, automation and test in Europe. ACM, 2008, pp. 1172-1177. [19] Li, Yi-Hua, et al. 'Capture-power-safe test pattern determination for at-speed scan-based testing.' IEEE Transactions on computer-aided design of integrated circuits and systems 33.1 (2014): 127-138. [20] Yu-Cheng Liu, Cheng-Yu Han, Shih-Yao Lin, and James Chien-Mo Li, “PSN-aware Circuit Test Timing Prediction using Machine Learning,” Proc. IET Computers & Digital Techniques, 2016. [21] Ma, Junxia, Jeremy Lee, and Mohammad Tehranipoor. 'Layout-aware pattern generation for maximizing supply noise effects on critical paths.' 2009 27th IEEE VLSI Test Symposium. IEEE, 2009, pp. 221-226. [22] Ma, Junxia, and Mohammad Tehranipoor. 'Layout-aware critical path delay test under maximum power supply noise effects.' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30.12 (2011): 1923-1934. [23] Miyase, Kohei, et al. 'Identification of high power consuming areas with gate type and logic level information.' 2015 20th IEEE European Test Symposium (ETS). IEEE, 2015, pp. 1-6. [24] Shepard, Kenneth L., and Vinod Narayanan. 'Noise in deep submicron digital design.' Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design. IEEE Computer Society, 1997, pp. 524-531. [25] Tehranipoor, Mohammad, and Kenneth M. Butler. 'Power supply noise: A survey on effects and research.' IEEE Design & Test of Computers 2.27 (2010): 51-67. [26] Wang, Jing, et al. 'Power supply noise in delay testing.' 2006 IEEE International Test Conference. IEEE, 2006, pp.1-10. [27] Wen, Xiaoqing, et al. 'Low-capture-power test generation for scan-based at-speed testing.' IEEE International Conference on Test, IEEE, 2005, pp. -1028. [28] Wen, Xiaoqing, et al. 'Critical-path-aware X-filling for effective IR-drop reduction in at-speed scan testing.' Proceedings of the 44th annual Design Automation Conference. ACM, 2007, pp. 527-532. [29] Wen, Xiaoqing, et al. 'On pinpoint capture power management in at-speed scan test generation.' 2012 IEEE International Test Conference. IEEE, 2012, pp. 1-10. [30] Yamato, Yuta, et al. 'A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation.' 2012 IEEE International Test Conference. IEEE, 2012, pp.1-8. [31] Ye, Fangming, et al. 'On-chip voltage-droop prediction using support-vector machines.' 2014 IEEE 32nd VLSI Test Symposium (VTS). IEEE, 2014, pp. 1-6. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18856 | - |
| dc.description.abstract | 過大的電源供應雜訊(如壓降)會造成電路時序的錯誤，然而要模擬電源供應的雜訊需要很長的時間，尤其在電路設計的過程，會需要很多次的模擬。本論文提出了使用機器學習的方法建立一個工程變更命令前的預測模型，在電路工程變更命令後，我們使用之前的預測模型預測現在電路的壓降，由於改版前後的電路很相似，預測模型的誤差很小。電路中有非常多的邏輯閘，我們可以很輕易從電路中得到大量的資料給機器學習。我們提出了七個特徵抽取的方法，這些方法都是簡單並且能在大電路中實現。我們在三百萬邏輯閘工業用真實電路的實驗結果顯示，預測壓降的誤差僅有3.7mV，相關係數為0.55，並且加速了30倍。我們提出的方法可以省下非常多的電路壓降模擬時間。 | zh_TW |
| dc.description.abstract | Excessive power supply noise (PSN), such as IR drop, can cause timing violation in VLSI chips. However, simulation PSN takes a very long time, especially when multiple iterations is needed in IR drop signoff. In this thesis, we propose a machine learning technique to build an IR drop prediction model based on circuits before ECO (engineer change order) revision. After revision, we can re-use this model to predict the IR drop of the revised circuit. Because the previous circuit(s) and the revised circuit are very similar, the model can be applied with small error. Since there are many cells on a die, after each IR drop analysis, we can easily obtain many IR drop data to train the machine learning model. We proposed seven feature extractions, which are simple and scalable for large designs. Our experiment results show that prediction accuracy (average error 3.7mV) and correlation (0.55) are very high for a three million-gate real design. The run time speedup is up to 30X. The proposed method is very useful for designers to save the simulation time when fixing the IR drop problem. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T01:37:55Z (GMT). No. of bitstreams: 1 ntu-105-R03943090-1.pdf: 1905291 bytes, checksum: d36868d84b8fbe2ec4c3d43d39f96789 (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | 致謝 i
摘要 ii Abstract iii Table of Contents iv List of Figures v List of Tables vi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Proposed Technique 4 1.3 Contributions 6 1.4 Organization 6 Chapter 2 Background 7 2.1 Statistical IR drop Prediction 7 2.2 Machine Learning IR drop Prediction 10 2.3 Dynamic IR drop Analyzer 12 Chapter 3 Proposed Techniques 14 3.1 Overall Flow 14 3.2 Cell Sampling 15 3.3 Feature Extraction 16 3.3.1 Power Features 17 3.3.2 Physical Features 18 3.3.3 Via Feature 20 3.4 Machine Learning Technique 21 Chapter 4 Experimental Results 24 4.1 IR drop Prediction before ECO 25 4.2 IR drop Prediction after ECO 28 4.3 Runtime Comparison 33 Chapter 5 Conclusion 35 References 36 | |
| dc.language.iso | en | |
| dc.title | 用機器學習預測工程變更命令後的電路壓降 | zh_TW |
| dc.title | IR Drop Prediction of ECO-Revised Circuits Using Machine Learning | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 105-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃俊郎(Jiun-Lang Huang),呂學坤(Shyue-Kung Lu) | |
| dc.subject.keyword | 壓降分析,機器學習, | zh_TW |
| dc.subject.keyword | power supply noise,IR drop analyzer,machine learning, | en |
| dc.relation.page | 39 | |
| dc.identifier.doi | 10.6342/NTU201603790 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2016-12-08 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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