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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李建模(Chien-Mo Li) | |
| dc.contributor.author | Yu-Ching Li | en |
| dc.contributor.author | 李昱慶 | zh_TW |
| dc.date.accessioned | 2021-06-08T01:37:47Z | - |
| dc.date.copyright | 2017-02-08 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-12-26 | |
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[Nassif 2008] S. Nassif., “Power grid analysis benchmarks,” Asia and South Pacific Design Automation Conference, Mar. 2008, pages 376–381. [Nilsson 2001] J.W. Nilsson, and S.A. Ridel, “Electric Circuits,” 2001 [Okumura 2010] T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, and M. Hashimoto, “Gate Delay Estimation in STA under Dynamic Power Supply Noise,” Proc. of Asia and South Pacific Design Automation Conference, 2010. [Peng 2010] K. Peng, Y. Huang, R. Guo, W. -T. Cheng, and M. Tehranipoor, “Emulating and diagnosing IR-drop by using dynamic SDF,” Proc. of Asia and South Pacific Design Automation Conference, 2010, pp. 511-516. [PrimeTime 2004] PrimeTime static timing analysis - synopsys, “http://www.synopsys.com/tools/implementation/signoff/documents/primetime_ds.pdf” [Qian 2003] H. Qian, S. R. Nassif, and S. S. Sapatnekar, “Random Walks in a Supply Network,” Proceedings of the IEEE/ACM Design Automation Conference, June 2003, pp. 93–98. [Saleh 2000] R. Saleh, S. Z. Hussain, S. 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Kwai, “A Power Delivery Network (PDN) Engineering Change Order (ECO) Approach for Repairing IR-Drop Failures after the Routing Stage,” International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2014. [Wang 2005] J. Wang, X. Lu, W. Qiu, Z. Yue, S. Fancler, W. Shi, and D. M. H. Walker, “Static Compaction of Delay Tests Considering Power Supply Noise,” Proc. of VLSI Test Symposium, May 2005, Palm Springs, CA, pp. 235-240. [Wang 2006] J. Wang, D. M. H. Walker, A. Majhi, B. Kruseman, G. Gronthoud, L. E. Villagra, P. v. d. Wiel, and S. Eichenberger, “Power supply noise in delay testing,” Proc. of Int’l Test Conf., 2006, pp. 1-10. [Zhong 2005] Y. Zhong, and M. D. F. Wong, “Fast Algorithms for IR Drop Analysis in Large Power Grid,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, Nov. 2005, pp. 351–357. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18847 | - |
| dc.description.abstract | 本論文提出一種自動化的方法來診斷造成電源供應雜訊違規(Power-Supply-Noise violations or PSN violations)的風險元件(risky cells)。我們還可以找到工程變更命令(Engineering Change Order or ECO)，如:調整大小(resize)或移動(move)風險元件以修復電源供應雜訊違規。我們應用重疊原理(superposition principle)將診斷和修復建模為線性規劃問題(linear programming)。我們不僅考慮電源供應雜訊約束，還考慮時序約束，以確保我們可以修復所有電源供應雜訊違規，而不會導致新的時序違規。有了我們的診斷結果，IC設計師可以花費很少的代價執行工程變更命令。實驗結果顯示，我們可以用只有不到2％的候選元件(candidate cell)修復所有電源供應雜訊違規。 | zh_TW |
| dc.description.abstract | This thesis proposes an automatic method to diagnose risky cells that are responsible for PSN (Power Supply Noise) violations. We can also find ECO (Engineering Change Order) method (resize or move) to perform on risky cells to repair PSN violations. We apply superposition principle to model the diagnosis and repair as a linear programming problem. We consider not only PSN constraints but also timing constraints to make sure that we can repair all PSN violations without causing new timing violations. With our diagnosis result, designers can perform ECO with very little circuit modification. The experimental results show that we can repair all PSN violations with only less than 2% of all candidate cells. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T01:37:47Z (GMT). No. of bitstreams: 1 ntu-105-R03943080-1.pdf: 1119148 bytes, checksum: 14b308b1afe64bb67172ac5e951d00b9 (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | 誌謝 i
中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vi LIST OF TABLES vii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Proposed technique 3 1.3 Contribution 4 1.4 Organization 5 Chapter 2 Background 6 2.1 Superposition principle 6 2.2 Prior work of PSN diagnosis and PSN violation repair 8 Chapter 3 Proposed Techniques 10 3.1 Overall flow 10 3.2 Identify candidate cells 12 3.3 Analyze ∆contribution 12 3.4 Diagnose risky cells 14 3.4.1 Linear programming model of cell resizing 14 3.4.2 Linear programming model of cell moving 15 3.4.3 Example of linear programming result 16 3.5 Engineering Change Order (ECO) 18 3.6 PSN and timing check 18 Chapter 4 Experimental Results 19 4.1 Experimental setup 19 4.2 Resize experimental result 21 4.3 Move experimental result 24 4.4 Resize result vs move result 26 4.5 Timing result 27 Chapter 5 Conclusion and Future Work 28 Reference 29 Appendix 34 | |
| dc.language.iso | en | |
| dc.title | 針對造成嚴重電源供應雜訊之元件診斷與修改 | zh_TW |
| dc.title | Diagnosis and Repair of Cells (DRC) Responsible for Power-Supply-Noise Violations | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 105-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 方家偉(Eric Fang),黃俊郎(Jiun-Lang Huang) | |
| dc.subject.keyword | 電源供應雜訊,診斷,修復,線性規劃,重疊原理, | zh_TW |
| dc.subject.keyword | power-supply-noise,diagnosis,repair,linear programming,superposition, | en |
| dc.relation.page | 35 | |
| dc.identifier.doi | 10.6342/NTU201603852 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2016-12-27 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-105-1.pdf 未授權公開取用 | 1.09 MB | Adobe PDF |
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