可適性偏壓線性化之CMOS射頻功率放大器

Abstract

最近幾年來，智慧型手機和手持裝置的迅速普及，在行動通訊系統裡面，隨著第二代、第三代到目前第四代行動通訊逐漸變得普及，智慧型手機已經成為人手必備的電子產品之一。而自從長期演進技術(Long Term Evolution, LTE)行動通訊技術由第三代合作夥伴計畫(3rd Generation Partnership Project, 3GPP)提出至今，其適用的頻帶相當多，而依據各個國家地區選擇的頻帶則不盡相同，且為了因應 LTE 資料傳輸速度的增加和使用頻寬的增大，對於行動通訊裝置中的射頻功率放大器(Radio-Frequency Power Amplifiers, RF PAs) 所帶來的挑戰即為高效率、高線性度和支援多模多頻(Multi-mode Multi-band)的設計架構。 本論文主旨在於改善射頻功率放大器之線性度，並使用互補式金屬氧化物半導體(Complementary Metal-Oxide-Semiconductor, CMOS)製程實現全積體化高效率高線性度之CMOS射頻功率放大器，在架構上採用堆疊式功率放大器(Stacked-FET Power Amplifier)，並藉由可適性偏壓電路(Adaptive Bias Circuit)根據不同輸入訊號大小改變電晶體閘極偏壓，達到改善射頻功率放大器線性度之效果。第一部分使用0.13微米CMOS製程實現單級射頻功率放大器，而第二部分使用0.13微米CMOS製程實現雙級射頻功率放大器。 第一部分使用0.13微米CMOS製程實現包含可適性偏壓電路之單級射頻功率放大器，晶片面積為 0.98 × 1.23 mm2 ，根據量測結果，在4.8 V供應電壓下，其單頻(CW)在1.95 GHz時射頻功率放大器之功率增益為 16.09 dB，1-dB增益壓縮點輸出功率(P1dB)為21.87 dBm，功率附加效率(PAE)在P1dB 時為 19.41 %，最大PAE為 20.96 %，此時輸出功率為 23 dBm。 第二部分使用0.13微米CMOS製程實現包含可適性偏壓電路之雙級射頻功率放大器，並加上增益補償電路和改進輸出匹配網路，晶片面積為 0.99 × 1.25 mm2 ，根據模擬結果，在4.8 V供應電壓下，其單頻(CW)在1.95 GHz時射頻功率放大器之功率增益為 32.69 dB，P1dB為28.41 dBm，PAE在P1dB時為 46.37 %，最大PAE為 47.92 %，此時輸出功率為 29.08 dBm。

With increasing popularity of the mobile communication system which evolves from the second generation, third generation to the fourth generation, smartphones have become one of the must-have Electronics products. Since the Long Term Evolution (LTE) technology has been proposed by the 3rd Generation Partnership Project (3GPP), the LTE standard covers a range of many different bands. According to the different LTE bands in the different countries, and in response to the increase of the LTE data rates and the increase of the bandwidth, the challenge of the radio-frequency power amplifier (RF PA) design in the mobile communication devices is high efficiency, high linearity, and support for multi-mode and multi-band. This thesis proposed a way to improve the linearity of the RF PAs which are implemented in Complementary Metal-Oxide-Semiconductor (CMOS) technology. The stacked-FET structure PA is used in this work and the linearity of the RF PA is improved by the adaptive bias circuit which the gate bias voltage of the transistor can be changed according to different input signal level. The first part implemented a single-stage RF PA using 0.13 m CMOS technology and the second part implemented a two-stage RF PA using 0.13 m CMOS technology. The single-stage RF PA is implemented in 0.13 m CMOS technology, including the adaptive bias circuit. The Chip size is 0.98 × 1.23 mm2. The PA was tested under a continuous-wave (CW) input at 1.95 GHz and a supply voltage of 4.8 V. The measured small-signal gain is 16.09 dB, At the 1-dB compression point, the output power (P1dB) is 21.84 dBm with a 19.41 % power-added efficiency (PAE). A maximum PAE is 20.96 % with a 23.51 dBm output power. The two-stage RF PA is implemented in 0.13 m CMOS technology, including the adaptive bias circuit, the gain compensation circuit and the improved output matching network. The Chip size is 0.99 × 1.25 mm2. The PA was simulated under a CW input at 1.95 GHz and a supply voltage of 4.8 V. The simulated small-signal gain is 32.69 dB. The P1dB is 28.41 dBm with a 46.37 % PAE.A maximum PAE is 47.92 % with a 29.08 dBm output power.