請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18719
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 劉致為 | |
dc.contributor.author | Tai-Cheng Shieh | en |
dc.contributor.author | 謝岱澄 | zh_TW |
dc.date.accessioned | 2021-06-08T01:21:36Z | - |
dc.date.copyright | 2014-09-03 | |
dc.date.issued | 2014 | |
dc.date.submitted | 2014-08-07 | |
dc.identifier.citation | [1] Moore, G.E., Cramming more components onto integrated circuits (Reprinted from Electronics, pg 114-117, April 19, 1965). Proceedings of the Ieee, 1998. 86(1): p. 82-85.
[2] C. Auth, C.A., A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarmane, T. Ghani, T. Glassman, R. Grover, W. Han, , et al. A 22nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, Self-Aligned Contacts and High Density MIM Capacitors in VLSI. 2012. [3] Colinge, J.P., Multi-gate SOI MOSFETs. Microelectronic Engineering, 2007. 84(9-10): p. 2071-2076. [4] R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. L. Blanc, “Design of ion-implanted MOSFET’s with very small physical dimensions,” IEEE J. Solid-state Circuits, vol. SC-9, pp. 256-268, 1974 [5] J. R. Brews, W. Fichtner, E. H. Nicollian, and S. M. Sze, “Generalized guide for MOSFET miniaturization,” IEEE Electron Device Len.,vol. EDL-1, pp. 2 4 , 1980. [6] P. Chatterjee, W. R. Hunter, T. C. Holloway, and Y. T. Lin, “The impact of scaling laws on the choice of n-channel or p-channel for MOS VLSI,” IEEE Electron Device Lett., vol. EDL-1, pp. 220-223. 1980. [7] G. Baccarani, M. R. Wordeman, and R. H. Dennard, “Generalized scaling theory and its application to a 114 micrometer MOSFET design,” IEEE Trans. Electron Devices, vol. ED-31, pp. 4 5 2 4 6 2 , 1984. [8] T. Y. Chan, P. K. KO, and C. Hu, “Dependence of channel electric field on device scaling,” IEEE Electron Device Lett., vol. EDL-6, pp. 551-553, 1985. [9] J. P. Colinge, M. H. Gao, A. R-Rodriguez, and C. Claeys, “Silicon- on-insulator gate-all-around device,” in I990 IEDM Tech. Dig., pp. 595-598. [10] J. Brini, M. Benachir, G. Ghibaudo, and F. Balestra, “Threshold slope of the volume-inversion MOS transistor,” ZEE Proc. G, vol. 138, pp. 133-136, 1991. [11] K. Suzuki, S. Satoh, T. Tanaka, and S. Ando, “Analytical models for symmetric thin-film double-gate silicon-on-insulator metal-oxide-semiconductor -field-effect-transistors,” Jpn. J. Appl. Phys., vol. 32, pp. 4916-4922, 1993. [12] S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981. [13] X. Tang, V. K. De, and J. D. Meindl, “Intrinsic MOSFET parameter fluctuations due to random dopant placement,” IEEE Trans. VLSI Technol., vol. 5, pp. 369–376, Dec. 1997. [14] Kunihiro Suzuki, Member, IEEE, and Toshihiro Sugii, “Analytical Models for n+-p + Double-Gate SO1 MOSFET's”, IEEE Train. on electron devices, vol. 42, no. 11, Nov. 1995 [15] Y. Taur, “Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs,” IEEE Trans. Electron Devices, vol. 48, pp. 2861–2869, Dec. 2001. [16] Francis, PASCALE, Terao, A., Flandre, DENIS, & Van de Wiele, FERNAND (1995). “Moderate inversion model of ultrathin double-gate nMOS/SOI transistors. Solid-state electronics”, 38(1), 171-176. [17] Y.Yuan Taur, “An analytical solution to a double-gate MOSFET with undoped body,” IEEE Electron Device Lett., vol. 21, pp. 245–247, May 2000. [18] Qiang Chen, Evans M. Harrell, II, and James D. Meindl, “A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 7, JULY 2003 [19] C.-H. Lin, R. Kambhampati, R. J. Miller, T. B. Hook, A. Bryant, W. Haensch, P. Oldiges, I. Lauer, T. Yamashita, V. Basker, T. Standaert, K. Rim, E. Leobandung, H. Bu, M. Khare, “Channel Doping Impact on FinFETs for 22nm and Beyond”, 2012 Symposium on VLSI Technology Digest of Technical Papers. [20] A. Ortiz-Conde, F.J. Garcıa Sanchez, J.J. Liou, A. Cerdeira , M. Estrada , Y. Yue, “A review of recent MOSFET threshold voltage extraction methods” Microelectronics Reliability 42 (2002) 583–596 [21] J. P. Colinge, C. W. Lee, N. Dehdashti Akhavan, R. Yan, I. Ferain, P. Razavi, A. Kranti, R. Yu “Semiconductor-On-Insulator Materials for Nanoelectronics Applications”, Engineering Materials 2011, pp 187-200 [22] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neal, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,” Nat. Nanotech- nol., vol. 5, no. 3, pp. 225–229, Mar. 2010. [23] C.-W. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, and J. P. Colinge, “Performance estimation of junctionless multigate transistors,” Solid-State Electron., vol. 54, no. 2, pp. 97–103, Feb. 2010. [24] A. Kranti, R. Yan, C.-W. Lee, I. Ferain, R. Yu, N. D. Akhavan, P. Razavi, and J. P. Colinge, “Junctionless nanowire transistor (JNT): Properties and design guidelines,” Solid-State Electronics 65–66 (2011) 33–37 [25] Park, C. H., Ko, M. D., Kim, K. H., Sohn, C. W., Baek, C. K., Jeong, Y. H., & Lee, J. S. (2011, June). “Comparative study of fabricated junctionless and inversion-mode nanowire FETs.” In Device Research Conference (DRC), 2011 69th Annual (pp. 179-180). IEEE. [26] C. W. Lee, I. Ferain, N. D. Akhavan, P. Razavi, R. Yan, R. Yu, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, S. Gheorghe, R. Murphy, and J. P. Colinge, “Short-channel junctionless nanowire transistors,” in Proc. SSDM, 2010, pp. 1044–1045. [27] Thompson, S.E., et al., A 90-nm logic technology featuring strained-silicon. IEEE Transactions on Electron Devices, 2004. 51(11): p. 1790-1797. [28] Jacoboni, C., Canali, C., Ottaviani, G., & Alberigi Quaranta, A. (1977). A review of some charge transport properties of silicon. Solid-State Electronics, 20(2), 77-89. [29] Soree, B., & Magnus, W. (2009, March). “Silicon nanowire pinch-off FET: basic operation and analytical model”. In Ultimate Integration of Silicon, 2009. ULIS 2009. 10th International Conference on (pp. 245-248). IEEE. [30] Yuan Taur, Tak H. Ning: “Fundamental of Mordern VLSI Devices”, 1998 [31] S. M. Sze and K. K. Ng: “Physics of Semiconductor Devices” 3rd ed., 2007 [32] J. Robertson and B. Falabretti, J. Appl. Phys. 100, 014111, 2006 [33] Hsu, S. H., Chu, C. L., Tu, W. H., Fu, Y. C., Sung, P. J., Chang, H. C., ... & Yang, F. L. (2011, December). Nearly defect-free Ge gate-all-around FETs on Si substrates. In Electron Devices Meeting (IEDM), 2011 IEEE International (pp. 35-2). IEEE. [34] Lee, C. W., Ferain, I., Kranti, A., Akhavan, N. D., Razavi, P., Yan, R., ... & Colinge, J. P. (2010, September). Short-channel junctionless nanowire transistors. In Proc. SSDM (pp. 1044-1045). [35] I-Hsieh Wong et al, “High Performance Junctionless In-situ Doped Ge Gate-all-around PFETs on Si”, ISDRS 2013. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18719 | - |
dc.description.abstract | 隨著摩爾定律的規則,半導體元件的尺寸持續微縮。近幾年,將傳統的元件的尺 寸按比例縮小的方式已經達到極限。為了要繼續符合摩爾定律的需求,微縮尺寸 的方向朝著以更換有著更高載子遷移率的通道材料以及創新元件結構前進。因此 鍺或其他三五族的通道材料成為近幾年熱門的研究題目,在 22nm 奈米製程結點開 始,新的 3D 鰭式電晶體結構開始取代傳統的平面式電晶體結構。 本論文中,我們利用 TCAD 電腦輔助模擬軟體來建立出雙閘極電晶體的臨界電壓 模型,並且考慮了不同通道濃度、通道寬度的影響,並且闡述其元件物理的特性。 此外也進行了在奈米尺寸具有優勢的無接面環繞式閘極電晶體的模擬與探討其物 理特性與優勢,之後更實際與真實元件作比對,並提出電晶體的改良設計方案。 | zh_TW |
dc.description.abstract | Base on Moore's Law, the size of semiconductor devices continued scaling. In recent years, the conventional element method has been approached to its fundamental limit. In order to continue to follow Moore's Law, high mobility meterials and new device structures has been investigated. Therefore, germanium and other III-V channel materials become a popular research topic in recent years. Starting at 22nm tecnology node, new 3D finFET structure began to replace the traditional planar transistor structure.
In this thesis, we use TCAD simulation to create threshold voltage model of a double gate transistors. The parameter such as different channels concentration and channel width are considered in this model. The device physic of double gate transistor is also investigated. Junctionless GAAFETs are also simulated to discuss the advantages. By fitting a real junctionless GAAFETs device, the device physic can be verify and proposed design solutions and improve the design of transistors. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T01:21:36Z (GMT). No. of bitstreams: 1 ntu-103-R01943057-1.pdf: 5339525 bytes, checksum: 7d1690ac9e250827f133ad9ce1b6c3a3 (MD5) Previous issue date: 2014 | en |
dc.description.tableofcontents | 口試委員會審定書 #
Related Publication (相關論文發表) ii 誌謝 iii 中文摘要 iv ABSTRACT v CONTENTS vi LIST OF FIGURES viii LIST OF TABLES xii Chapter 1 Introduction 1 Chapter 2 Threshold Voltage Modeling of Double Gate MOSFETs 4 2.1 Introduction 4 2.2 VTH Extraction by Constant-Current Method 5 2.3 Band Diagram of Lightly Doped Double Gate MOSFETs Near Threshold Condition 6 2.4 Threshold Voltage Modeling of Lightly Doped Double Gate MOSFETs 8 2.5 Device Structure of Simulation 9 2.6 Band Diagram and Carrier Distribution of Double Gate MOSFETs 10 2.7 Threshold Voltage Modeling of Double Gate MOSFETs with Moderate Channel Doping 12 2.8 Threshold Voltage Modeling of Heavily Doped Double Gate MOSFETs 15 2.9 Quantum Effect of Double Gate MOSFETs on VTH 18 2.10 VTH Modeling with Quantum Effect 19 Chapter 3 Device Physics of Junctionless Ge GAAFETs 22 3.1 Introduction 22 3.1.1 Device Structure of the Junctionless Transistor 23 3.1.2 Conduction Mechanism of the Junctionless Transistor 25 3.1.3 Mobility Issue of MOSFETs 27 3.2 Threshold Voltage of Junctionless FETs 29 3.3 Simulation Structure and Parameter Set Up 31 3.4 Subthreshold Swing with Different Channel Radius/Doping Configuration 32 3.5 Impact of Interface Traps on Subthreshold Swing 38 3.5.1 Interface Traps distribution of TCAD simulation 38 3.5.2 Subthreshold Swing of Junctionless MOSFETs with Dit. 41 Chapter 4 Simulation of Junctionless Ge GAA p-FETs 50 4.1 Introduction 50 4.2 Device architecture and simulation parameter extraction 50 4.3 Design region and short channel effect of Junctionless Ge GAA p-FETs 53 4.4 Junctionless GAAFETs with Gate-Modulated S/D Structure 58 4.5 Non-uniform channel of junctionless GAAFETs 61 Chapter 5 Summary and Future Work 64 5.1 Summary 64 5.2 Future Work 66 REFERENCE 67 | |
dc.language.iso | en | |
dc.title | 雙閘極電晶體臨界電壓模型模擬與無接面環繞式閘極
鍺電晶體之特性模擬 | zh_TW |
dc.title | Threshold Voltage Modeling of Double Gate MOSFETs and Simulation of Junctionless Ge GAAFETs | en |
dc.type | Thesis | |
dc.date.schoolyear | 102-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 林鴻志,張廖貴術,李峻霣 | |
dc.subject.keyword | 雙閘極電晶體,無接面環繞式閘極電晶體, | zh_TW |
dc.subject.keyword | Double gate MOSFETs,Junctionless Gate-All-Around FETs, | en |
dc.relation.page | 70 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2014-08-07 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-103-1.pdf 目前未授權公開取用 | 5.21 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。