50~200億位元之可適性線性等化器及決策回授等化器

Abstract

近幾年來，除了資料傳輸速度的高速成長之外，廣範圍的資料也被要求於各種多媒體和攜帶式裝置的應用。隨著傳輸速度的提升，許多嚴重的問題也浮現出來，相對於資料傳輸的速度，傳輸通道的有限頻寬就是其中一個問題，這個問題會使得原本傳送的訊號失真，導致嚴重的符際干擾並且使位元錯誤率升高。為了解決符際干擾問題，等化器被廣泛的運用來解決此問題。然而，傳輸通道的長度以及材質通常會隨著應用而不同。因此，在最近的通訊系統中，等化器也通常會伴隨著一個可適性的演算法。而在廣範圍的資料傳輸中，功率的效率的議題也開始被重視。 本論文最主要分成兩個部分。第二章提出一個介紹一個具有功率可調性的可適性線性等化器。在比較低的資料傳輸時，功率可調性可以提升功率效率。我們也提出一個利用計算訊號轉換次數的可適性演算法。此電路實作於40-nm CMOS製程。 第三章是介紹一個利用電荷導向式邏輯電路組成的決策回授等化器。為了降低系統的功率消耗，我們的設計使用了電荷導向式邏輯電路。並且利用SSLMS演算法來自動調整決策回授等化器的補償係數。此電路實作於40-nm CMOS製程。

In recent years, in addition to the fast growing in data rate, wide-range data is also required in the applications of various multimedias and portable devices. As the data rate keeps rising, many significant problems appear. One is that the bandwidth is limited compared to the data rate. It will result a significant inter symbol interference (ISI) to degrade the bit error rate (BER). In order to deal with ISI, equalizers are widely adopted. However, the length or the material of the communication channel may be different depending on the application. Therefore, an adaptive algorithm with the equalizer is more popular in recent communication systems. In wide-range data rate application, power efficiency issue is also concerned. This thesis is mainly divided into two parts. In Chapter 2, a 5-20 Gb/s power scalable adaptive continuous-time linear equalizer (CTLE) architecture is proposed. We use a power scalable technique to improve the power efficiency for slow data rate. We also propose an adaptive algorithm using edge counting. This circuit is implemented in 40-nm CMOS process. A 5-20 Gb/s adaptive charge-steering decision-feedback equalizer (DFE) is presented in chapter 3. To lower power consumption of the system, charge-steering logic circuit is adopted in this design. We use sign-sign least mean square (SSLMS) algorithm to adjust the DFE’s taps adaptively. This circuit is implemented in 40-nm CMOS process.