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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 簡韶逸(Shao-Yi Chien) | |
dc.contributor.author | Yi-Chi Lai | en |
dc.contributor.author | 賴奕齊 | zh_TW |
dc.date.accessioned | 2021-06-08T01:00:55Z | - |
dc.date.copyright | 2015-02-04 | |
dc.date.issued | 2014 | |
dc.date.submitted | 2014-12-04 | |
dc.identifier.citation | [1] Neil Weste and David Harris, CMOS VLSI Design: A Circuits and Systems Perspective. Pearson Education,2005.
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[31] J.S. Kim, C.S. Oh, et al., 'A 1.2V 12.8GB/s 2Gb Mobile Wide-I/O DRAM with 4x128 I/Os Using TSV-Based Stacking,' Int. Solid-State Circuits Conf., pp. 496 - 498 ,Feb. 2011. [32] H. Yamauchi, 'Variation-Tolerant SRAM Circuit Designs,' ISSCC Tutorial 2009. [33] M.-F. Chang, S.-M. Yang, and K.-T. Chen, 'Wide-VDD embedded asynchronous SRAM with dual-mode self-timed technique for dynamic voltage systems,' IEEE Trans. Circuits and Syst. I, vol. 56, no. 8, pp. 1657-1667, Aug. 2009 [34] K. Osada, S. Jinuk Luke, M. Khan, Y. Liou, K. Wang, K. Shoji, K. Kuroda, S. Ikeda, and K. Ishibashi, 'Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell,' IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1738-1744, Nov. 2001 [35] H. Nambu, K. Kanetani, K. Yamasaki, K. Higeta, M. Usami, Y. Fujimura, K. Ando, T. Kusunoki, K. Yamaguchi, and N. Homma, 'A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM,' IEEE J. Solid-State Circuits, vol. 33, no. 11, pp. 1208-1219, Nov. 1998. [36] B. S. Amrutur and M. A. Horowitz, 'A replica technique for wordline and sense control in low-power SRAM's,' IEEE J. Solid-State Circuits, vol. 33, no. 8, pp. 1208-1219, Aug. 1998. [37] Meng-Fan Chang, Wei-Cheng Wu, Chih-Sheng Lin et al., ' A Larger Stacked Layer Number Scalable TSV-based 3D-SRAM for High-Performance Universal-Memory-Capacity 3D-IC Platforms,' in Symp. VLSI Circuit, vol., no., pp.74-75, 13-17 June 2011 [38] K. Takeuchi, T. Fukai, T. Tsunomura, A. T. Purta, A. Nishida, S. Kamohara, and T. Hiramoto, 'Understanding Random Threshold Voltage Fluctuation by Comparing Multiple Fabs and Technologies,' in IEDM Dig. Tech. Papers, pp. 467-470, Dec. 2007 [39] B. Wicht, T. Nirschl, D. Schmitt-Landsiedel, “Yield and speed optimization of a latch-type voltage sense amplifier,” IEEE J. Solid-State Circuits, vol. 39, no 7, pp. 1148-1158, July 2004. [40] J. David Irwin, A Brief Introduction to Circuit Analysis. Wiley, 2003. [41] David E. Johnson, Electric Circuits Analysis 3rd Edition. Wiley, 1997. [42] Verma, N., et al., 'A High-Density 45nm SRAM Using Small-Signal Non-Strobed Regenerative Sensing,' Proc. IEEE Int. Solid-State Circuits Conf., pp.380-621, 3-7 Feb. 2008 [43] Chandrakasan, et al., 'High density 45 nm SRAM using small-signal non-strobed regenerative sensing,' US:7746713 B2, June, 29, 2010 [44] Yong-Cheol Bae, Joon-Young Park et al., “A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with Input Skew Calibration and Enhanced Control Scheme,” Int. Solid-State Circuits Conf., pp. 44-46, FEB. 2012. [45] Joe Jeddeloh, Brent Keeth, “Hybrid Memory Cube New DRAM Architecture Increases Density and Performance,” in Symp. VLSI Technology, vol., no., pp.87-88, 2012 [46] Yong Liu, Wing Luk, “A Compact Low-Power 3D I/O in 45nm CMOS,” Int. Solid-State Circuits Conf., pp. 142-144, FEB. 2012. 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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18349 | - |
dc.description.abstract | 隨著製成演進,由於線電容線電阻與漏電流影響增加,使得我們難以持續追隨著摩爾定律。根據國際半導體技術路程組織所提出的超越摩爾定律路程,新的技術像是多閘極電晶體、奈米碳管、三維積體電路等方法被提出來,而我們選擇三維積體電路技術來解決上述這樣的問題。一種提供垂直連接的製程技術稱為矽晶穿孔,其已經成為三維堆疊元件的一個有前景的解決方案。
本論文我們提出了利用多晶矽傳輸且支援多層傳輸並且去除預充電機制的傳輸方法。三維記憶體主要將兩個完整記憶體堆疊起來並用矽晶穿孔做連接。此電路採用是主層與僕層的連接架構,上層的訊號透過矽晶穿孔傳到下層,傳統上如果是直接傳輸,當電路之輸入/輸出矽晶穿孔數量很大時,對於每個矽晶穿孔充電浪費很多功耗;故基於此議題,本設計提供一三維晶片感測及電荷共享方法以解決該問題。可以降低在矽晶穿孔傳輸介面上產生的功耗,以及利用偵測控制時脈達成支援三維堆疊多層之情形。 我們使用台積電九十奈米混合訊號製成來完成了一個由六萬四千字元所組成的三維靜態隨機存取記憶體,量測結果顯示在堆疊四層時比起單端輸出有30%的功耗降低。 | zh_TW |
dc.description.abstract | It’s difficult to keep following the Moore’s Law due to the larger effect of the wire resistance, wire capacitance and leakage current. According to the ITRS More-than-Moore Roadmap, the new type of technology should be developed such like FinFET, Carbon tube of 3D-IC. We choose 3D-IC to solve the mentioned problem. The TSV technology for vertical transmission is introduced to the 3D-IC process, and become a popular solution to the 3D-IC stacking issue.
In the thesis, we proposed a TSV-based multi-layer transmission with free-pre-charge operation scheme. 3D-SRAM is constructed with multi-layer whole memory array and TSV for stacking. This design follows the single master scheme to control the master layer and slave layer transmission. The traditional transmission such like single-ended would cost a lot of power due to rail-to-rail transmission, especially in the wild I/O situation. Although the differential transmission creates a small swing voltage to reduce the power consumption in TSV, the pre-charge cycle in every read operation would cost tremendous power, too. Our scheme provides a free-pre-charge architecture with charge recycle and tracking systems. The proposed 64kb 3D-SRAM was fabricated in TSMC 90nm mix-signal process with 2, 4, 8, 16 layers modeling ability. The proposed design 30% power reduction, compare to single-ended transfer scheme. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T01:00:55Z (GMT). No. of bitstreams: 1 ntu-103-R00943046-1.pdf: 12620041 bytes, checksum: 337c845a84167af6bcb0c4f98b3af410 (MD5) Previous issue date: 2014 | en |
dc.description.tableofcontents | 致謝 i
摘要 ii Abstract iii Contents iv List of Figures vii List of Tables x Acronyms xi Chapter1 Introduction 1 1.1 Motivation and Application for 3D-SRAM 1 1.2 Emerging Technology: 3D-IC 4 1.2.1 Die/Wafer Assembly 4 1.2.2 Bonding Styles 5 1.3 Thesis Organization 6 Chapter2 Characteristic and Analysis of ITRI 3D IC Process 7 2.1 Introduction to ITRI 3D IC Process 7 2.2 Introduction to different TSV Process 9 2.3 RC Characteristic Analysis for ITRI 3D Process 10 Chapter3 Architecture of 3D SRAM 13 3.1 Novel Architecture for 3D Memory Integrated Application 13 3.1.1 Conventional Direct Stacking and Master-Slave Architecture 14 3.1.2 Semi Master-Slave Architecture 16 3.1.3 3D Multi-Ported SRAM Arrays 17 3.1.4 3D Ultra-high Bandwidth Memory 20 3.1.5 3D System Integration Using Inductive-Coupling Link 22 3.2 Wide I/O Standard Design 25 3.2.1 Wide I/O standard 25 3.2.2 Wide I/O in 3D DRAM 25 Chapter4 Proposed Charge-Sharing Transfer Scheme 27 4.1 Concepts of Proposed Charge Sharing Scheme 27 4.2 Charge-Sharing Transfer Scheme 30 4.3 Self-Timed Tracking Scheme 34 4.4 Clamping circuit 38 Chapter5 Analyses and Comparisons of Charge-sharing Scheme 43 5.1 Speed Comparison of Charge-Sharing, Single End& STDT 43 5.1.1 Transfer Speed Using the Same Driver Size 43 5.2 Power Consumption of Charge sharing scheme 45 5.2.1 Power Consumptions compare to STDT scheme 46 5.2.2 Power Consumptions compare to Traditional Single-ended scheme 49 Chapter6 Macro Implementation 51 6.1 Architecture of Proposed 3D-SRAM 51 6.2 Test Chip Design 56 Chapter7 Experimental Results and Conclusions 58 7.1 Measurement Results 58 7.2 Conclusion of This Thesis 63 7.3 Future work 66 References 67 | |
dc.language.iso | en | |
dc.title | 一個利用矽晶穿孔支援多層傳輸省電策略之三維靜態隨機存取記憶體設計 | zh_TW |
dc.title | A TSV-Based with Multi-Layer Transmission for Low Power Strategy 3D SRAM Design | en |
dc.type | Thesis | |
dc.date.schoolyear | 103-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 李泰成(Tai-Cheng Lee),盧奕璋(Yi-Chang Lu),劉宗德(Tsung-Te Liu) | |
dc.subject.keyword | 三維記憶體,矽晶穿孔, | zh_TW |
dc.subject.keyword | 3DSRAM,TSV, | en |
dc.relation.page | 70 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2014-12-04 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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