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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18348完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李建模 | |
| dc.contributor.author | Shih-An Hsieh | en |
| dc.contributor.author | 謝詩安 | zh_TW |
| dc.date.accessioned | 2021-06-08T01:00:52Z | - |
| dc.date.copyright | 2015-02-04 | |
| dc.date.issued | 2014 | |
| dc.date.submitted | 2014-12-04 | |
| dc.identifier.citation | [Bainbridge 03] W. J. Bainbridge, W. B. Toms, D. A. Edwards, and S. B. Furber, “Delay-insensitive, point-to-point interconnect using m-of-n codes,” In Asynchronous Circuits and Systems, Proceedings. Ninth International Symposium on, pp. 132-140, 2003.
[Beerel 10] P. A. Beerel, R. O. Ozdag, and M. Ferretti, “A designer's guide to asynchronous VLSI,” Cambridge University Press, 2010. [Beest 02] F. Beest, A. Peeters, M. Verra, K. van Berkel, and H. Kerkhoff, “Automatic scan insertion and test generation for asynchronous circuits,” Proceedings of IEEE Test Conference, pp. 804-813, 2002. [Cheng 11] C. H. Cheng, and J. C. M. Li, “An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology,” Journal of Electronic Testing, pp. 193-201, Feb. 2011. [Fant 96] K.M. Fant and S.A. Brandt, “Null Conventional Logic: A complete and consistent logic for asyncrhonous digitlal circuit synthesis,” International Conference on Application-specific Systems, Architectures, and Processors, pp. 261-273, 1996. [Hoare 78] C. A. R. Hoare, “Communicating sequential processes,” Commun. ACM, vol 21, pp. 666-677, 1978. [Hulggard 95] H. Hulggard, S. M. Burn, G. Borriello, “Testing asynchronous circuits: a survey,” the VLSI Journal, pp 111-131, 1995. S. Feng, “Simulating and testing asynchronous circuits,“ Yale University, 2007. [Kakarla 08] S. Kakarla, and W. K. Al-Assadi, 'Testing of asynchronous NULL conventional logic (NCL) circuits,' In Region 5 Conference, IEEE , pp. 1-6, 2008. [Kang 99] Y. Kang, K. Huh, S. Kang, “New scan design asynchronous sequential circuit,” Proceedings of IEEE Asia Pacific Conference on ASIC, pp 355-358, 1999. [Kondratyev 02] A. Kondratyev, L. Sorensen, and A. Streich, 'Testing of asynchronous designs by 'inappropriate' means. Synchronous approach,' Proceedings of IEEE Asynchronous Circuits and Systems, Eighth International Symposium, pp. 171-180, Apr. 2002. [Lines 98] A.M. Lines, “Pipelined Asynchronous Circuits,” M. S. thesis, California Institute of Technology, Pasadena, CA, USA, 1998. [Marr 13] B. Marr, B. Degnan, P. Hasler, and D. Anderson, “Scaling energy per operation via an asynchronous pipeline,” IEEE Trans. Very Large Scale Integr. (VLSI) System, vol. 21, no. 1, pp. 141-151, Jan. 2013 [Moore 02] S. Moore, G. Taylor, R. Mullins, and P. Robinson, “Point to point GALS interconnect,” In Asynchronous Circuits and Systems, Proceedings. Eighth International Symposium on, pp. 69-75, 2002. [Petlin 95] O. A. Petlin, “Scan testing of asynchronous sequential circuits,“ Proceedings of Great Lakes Symposium on VLSI, pp 224-229, 1995. [Sparsø 01] J. Sparsø, S. Furber, “Principles of Asynchronous Circuit design – A system Perspective,” Kluwer Academic Publisher, 2001. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18348 | - |
| dc.description.abstract | 本論文一個針對雙軌非同步電路的測試技術：DR-scan。本文提出了一個完全掃描的可測試技術，其應用了非同步的雙軌邏輯電路的個編碼，達到掃描鍊在轉移時無需時脈。本文的可測試設計技術可以被應用在許多的實作方法，如：DIMS、NCL、PCHB。本技術應用了傳統的完全掃描自動測試圖樣產生器來產生高錯誤涵蓋率的測試圖樣。實驗結果顯示16位元線性管路乘法器的額外面積僅有9%。在非線性管路電路上的錯誤涵蓋率皆高於98%。 | zh_TW |
| dc.description.abstract | This thesis presents a test methodology, Dual-rail scan (DR-scan), for dual-rail asynchronous circuits. We propose a full-scan design for testability (DfT) technique, which uses all four codewords in dual-rail logic so that scan chains can be shifted without clock. Our DfT can be applied to various implementations, including delay insensitive minterm synthesis (DIMS), null conventional logic (NCL), and pre-charge half buffer (PCHB). DR-scan enables traditional full-scan automatic test pattern generation (ATPG) to generate high fault coverage test patterns. Experimental results show area overhead of 16-bit multiplier linear pipeline is only 9%. Fault coverage on non-linear pipeline circuits are higher than 98%. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T01:00:52Z (GMT). No. of bitstreams: 1 ntu-103-R01943138-1.pdf: 1381448 bytes, checksum: 00bf0db576d688e48e8c1c6d247882a0 (MD5) Previous issue date: 2014 | en |
| dc.description.tableofcontents | 口試委員會審定書 i
致謝 iii 摘要 iv Abstract v Table of Contents vi List of Figures viii List of Tables ix Chapter1 Introduction 1 1.1 Motivation 1 1.2 Proposed technique 2 1.3 Contribution 3 1.4 Organization 3 Chapter2 Background 5 2.1 Dual-rail asynchronous circuits 5 2.2 Past research in asynchronous testing 10 Chapter3 Dual-rail Scan 16 3.1 Scan latch 16 3.2 DR-scan operation 21 3.3 Timing assumption 24 Chapter4 Proposed Test Methodology 27 4.1 Circuit partition (Linear pipeline) 27 4.2 DfT Insertion (Linear pipeline) 29 4.3 ATPG 31 4.4 Non-linear pipeline 33 Chapter5 Experimental Results 37 Chapter6 Conclusion and Feature work 41 Reference 43 | |
| dc.language.iso | en | |
| dc.title | DR-scan: 針對雙軌非同步電路的測試技術 | zh_TW |
| dc.title | DR-scan: A Test Methodology for Dual-rail Asynchronous Circuits | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 103-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 江介宏,潘正聖 | |
| dc.subject.keyword | 非同步電路,雙軌邏輯電路,掃描鍊,可測試設計,測試圖樣產生, | zh_TW |
| dc.subject.keyword | Asynchronous circuits,Dual-rail logic,Scan chain,Design for testability,Test pattern generation, | en |
| dc.relation.page | 45 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2014-12-04 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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