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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳怡然 | |
| dc.contributor.author | Pei-Chun Wu | en |
| dc.contributor.author | 吳培鈞 | zh_TW |
| dc.date.accessioned | 2021-06-08T01:00:30Z | - |
| dc.date.copyright | 2015-02-04 | |
| dc.date.issued | 2014 | |
| dc.date.submitted | 2014-12-17 | |
| dc.identifier.citation | [1] X. Gao, E. Klumperink, M. Bohsali and B. Nauta, “A low noise subsampling PLL in which divider noise is eliminated and PD/CP noise is not multiplied by N2,” IEEE J. Solid-State Circuits, vol. 44, pp. 3253-3263, Dec. 2009.
[2] X. Gao, et al., “A 2.2GHz 7.6mW sub-sampling PLL with -126dBc/Hz in-band phase noise and 0.15psrms jitter in 0.18μm CMOS,” IEEE Int. Solid-State Circuits Conf. Tech. Dig, Feb. 2009, pp. 392-393. [3] X. Gao, E. Klumperink, G. Socci, M. Bohsali and B. Nauta, “Spur reduction techniques for phase-locked loops exploiting a sub-sampling phase detector,” IEEE J Solid-State Circuits, vol. 45, no. 9, pp. 1809-1821, Sep. 2010. [4] A. Shahani, et al., “Low-power dividerless frequency synthesis using aperture phase detector”, IEEE J.Solid-State Circuits, vol. 33, pp. 2232-2239, Dec. 1998. [5] D. Cai et al., “A 2.1-GHz PLL with -80dBc/ -74dBc reference spur based on aperture-phase detector and phase-to-analog converter,” Proc. IEEE ASSCC Symp. Dig., Nov. 2011, pp. 141-144. [6] D. Cai, et al., “A dividerless PLL with low power and low reference spur by aperture-phase detector and phase-to-analog converter,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol.60, no.1, pp. 37-50, Jan. 2013. [7] C.-W. Hsu, S.-A. Yu and P. R. Kinget, “A 2.2GHz PLL using a phase-frequency detector with an auxiliary sub-sampling phase detector for in-band noise suppression,” IEEE Custom Integrated Circuits Conf., Sept. 2011, pp. 1-4. [8] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol.33, no. 2, pp. 179-194, Feb. 1998. [9] S. Yeh, L. Jansson and I. Galton, “A multiple-crystal interface PLL with VCO realignment to reduce phase noise,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1795–1803, Dec. 2002. [10] B. Razavi, “A study of injection locking and pulling in oscillators,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1415-1424, Sep. 2004. [11] J. Lee and H. Wang, “Study of subharmonically injection-locked PLLs,” IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1539-1553, May 2009. [12] B. M. Helal, C.-M. Hsu, K. Johnson and M. H. Perrott, “A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop,” IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1391-1400, May 2009. [13] C.-F. Liang and K.-J. Hsiao, “An injection-locked ring PLL with self-aligned injection window,” IEEE Int. Solid-State Circuits Conf. Tech. Dig, Feb 2011, pp. 90-92. [14] Y.-C. Huang and S.-I. Liu, “A 2.4 GHz sub-harmonically injection locked PLL with self-calibrated injection timing,” IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2012, pp. 338–340. [15] I.-T. Lee, Y.-J. Chen, S.-I. Liu, C.-P. Jou, F.-L. Hsueh and H.-H. Hsieh, “A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing,” IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2013, pp. 414¬415. [16] Y.-C. Huang and S.-I. Liu, “A 2.4-GHz subharmonically injection-locked PLL with self-calibrated injection timing,” IEEE J. Solid-State Circuits, vol. 48, no. 2, pp. 417-428, Feb 2013. [17] I-T. Lee, K.-H. Zeng and S.-I. Liu, “A 4.8-GHz dividerless subharmonically injection-locked all-digital PLL with a FOM of -252.2 dB,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.60, no.9, pp. 547-551, Sep. 2013. [18] H.-Y. Chang, Y.-L. Yeh, Y.-C. Liu, M.-H. Li and K. Chen, “A low-jitter low-phase-noise 10-GHz sub-harmonically injection-locked PLL with self-aligned DLL in 65-nm CMOS technology,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 3, pp. 543-555, Mar. 2014. [19] J. Choi, W. Kim and K. Lim, “A spur suppression technique using an edge-interpolator for a charge-pump PLL,” IEEE Trans. on VLSI Syst., vol. 20, no. 5, pp. 969-973, May 2012. [20] C.-F. Liang, S.-H. Chen and S.-I. Liu, “A digital calibration technique for charge pumps in phase-locked systems,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 390-398, Feb 2008. [21] 陳信樺, “應用於手提式數位電視接收器之具邊頻改善頻率合成器”國立台灣大學電子工程學研究所碩士論文，2006. [22] 劉深淵,楊清淵, “鎖相迴路”, 滄海書局, 2006. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18340 | - |
| dc.description.abstract | 本地振盪器(local oscillator)在無線通訊系統中，扮演著很重要的角色。在射頻收發機中，通常是使用鎖相迴路系統作為本地振盪器。類比鎖相迴路至今已有相當長的發展歷史，在許多方面也已發展得趨於成熟，但許多特性仍有加以改進的空間，例如: 鎖定時間(settling time)、相位雜訊(phase noise)、參考突波(reference spur)等。其中相位雜訊的改善依舊是一個相當具有挑戰性的議題，針對此議題，也不斷地發展出新的技術加以改善。
近幾年針對相位雜訊改善發展出了許多新的技術，其中無除頻器之頻率合成器與次諧波注入鎖相迴路為兩種改善較為顯著的技術，然而這兩種技術中，仍有許多發展尚未完善之處，例如: 鎖相迴路中不同模式的切換、次諧波注入的相位對準等。現有的技術中，普遍使用手調的方式來進行切換與相位對準，為了改善此點，本論文提出了一個新型的架構，在能自動切換不同鎖定模式的同時，也能在次諧波注入時自動進行相位對準。 | zh_TW |
| dc.description.abstract | Local oscillator plays an important role in wireless communication system. In radio frequency transceivers, phase locked loops are frequently used as a local oscillator. The development of analog phase-locked loop has a long history, and it has certainly become very well developed. However, there are still plenty of requirements that need to be improved upon, such as settling time, phase noise, reference spur, etc. Among these requirements, phase noise is still a challenging issue. Since then, many new techniques have been developed in order to improve the phase noise performance.
Several new techniques have been created in recent years, two of which are worth noting here: dividerless phase locked loop and subharmonically injection locked phase locked loop. Both have seen great improvements in phase noise performance. However, there are still parts of the systems that are not well developed, such as switching between different modes, phase alignment of subharmonically injection locked PLL, etc. Nowadays people manual switch between modes and manually adjust for phase alignment. This paper proposes a new architecture which not only self-switches between different modes but also does the self-alignment for subharmonically injection locked PLL. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T01:00:30Z (GMT). No. of bitstreams: 1 ntu-103-R00943117-1.pdf: 8758604 bytes, checksum: 718adc09def447523940d5f3b55f9c4c (MD5) Previous issue date: 2014 | en |
| dc.description.tableofcontents | 摘要 I
ABSTRACT III 目錄 V CHAPTER 1 序論 1 1.1 動機 1 1.2 無除頻器及次諧波注入鎖相迴路 1 1.3 文獻回顧 3 1.3.1 無除頻器之頻率合成器 3 1.3.2 次諧波注入鎖相迴路 9 1.4 論文架構 16 CHAPTER 2 頻率合成器的基本原理 17 2.1 簡介 17 2.2 特性指標 18 2.2.1 相位雜訊(Phase Noise) 18 2.2.2 參考突波(Reference Spur) 20 2.3 鎖相迴路電路架構 21 2.3.1 相位頻率偵測器(Phase Frequency Detector) 21 2.3.2 充電泵和迴路濾波器(Charge Pump and Loop Filter) 24 2.3.3 壓控振盪器(Voltage-Controlled Oscillator) 27 2.3.4 除頻器(Divider) 27 2.4 鎖相迴路的線性模型 31 2.5 相位雜訊分析 33 2.5.1 輸入端雜訊 33 2.5.2 壓控振盪器的雜訊 35 2.6 鎖相迴路設計 36 2.6.1 二階鎖相迴路 36 2.6.2 三階鎖相迴路 39 CHAPTER 3 相位雜訊的抑制技術 43 3.1 無除頻器之頻率合成器 43 3.1.1 次取樣鎖相迴路(Sub-sampling PLL) 43 3.1.2 孔隙相位偵測器(Aperture Phase Detector) 47 3.2 次諧波注入鎖相迴路技術 52 3.2.1 次諧波注入之文獻回顧 52 3.2.2 次諧波注入分析 57 3.3 摘要 59 CHAPTER 4 無除頻器次諧波注入鎖定頻率合成器設計 60 4.1 電路規格與架構簡介 60 4.2 無除頻器之頻率合成器 62 4.2.1 孔隙相位偵測器 64 4.2.2 相位類比轉換器 66 4.2.3 充電泵 69 4.2.4 脈衝產生器(Pulse Generator) 71 4.2.5 鎖定偵測器 72 4.2.6 注入訊號產生器 74 4.3 鎖相迴路電路方塊 76 4.3.1 相位頻率偵測器 76 4.3.2 充電泵 78 4.3.3 四頻帶可注入式壓控振盪器 79 4.3.4 多模數可程式化除頻器 81 CHAPTER 5 電路模擬 83 5.1 行為模擬 83 5.2 模擬結果 83 5.2.1 鎖定過程 84 5.2.2 穩態結果 87 5.2.3 模態分析與比較 88 5.2.4 相位雜訊模擬方式 91 5.2.5 總結 92 CHAPTER 6 結論 94 參考文獻 95 | |
| dc.language.iso | zh-TW | |
| dc.title | 具次諧波相位自動對準技術之無除頻器次諧波注入頻率合成器 | zh_TW |
| dc.title | A Dividerless Subharmonically Injection Locked Frequency Synthesizer with Self Injected Signal Aligning | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 103-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 楊清淵,謝秉璇,陳昭宏 | |
| dc.subject.keyword | 鎖相迴路,相位雜訊,無除頻器頻率合成器,次諧波注入,相位對準, | zh_TW |
| dc.subject.keyword | Phase Locked Loop,Phase Noise,Dividerless Frequency Synthesizer,Subharmonically Injection Locked,Self-alignment, | en |
| dc.relation.page | 96 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2014-12-17 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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