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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18171完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李建模(Chien-Mo Li) | |
| dc.contributor.author | Po-Kai Hsieh | en |
| dc.contributor.author | 謝柏凱 | zh_TW |
| dc.date.accessioned | 2021-06-08T00:53:32Z | - |
| dc.date.copyright | 2015-08-11 | |
| dc.date.issued | 2015 | |
| dc.date.submitted | 2015-06-03 | |
| dc.identifier.citation | [1]K. Zhang, “ISSCC 2013: Memory trends”, 2013.
http://www.maltiel-consulting.com/ISSCC-2013-Memory-trends-FLash-NAND-DRAM.html [2]Arijit Raychowdhury, Saibal Mukhopadhyay, and Kaushik Roy, “A feasibility study of subthreshold SRAM across technology generations,” Computer Design: VLSI in Computers and Processors (ICCD'05), 2005 IEEE International Conference on, pp.417-422, Oct 2005. [3]Leland Chang et al., “Stable SRAM cell design for the 32 nm node and beyond,” in Symp. VLSI Technology Dig. Tech. Papers, Jun. 2005, pp. 128-129 [4]Milad Zamani, Sina Hassanzadeh, Khosrow Hajsadeghi and Roghayeh Saeidi, “A 32kb 90nm 9T-cell Sub-threshold SRAM with Improved Read and Write SNM,” Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2013 8th International Conference on, pp. 104-107, 2013 [5]Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, and Kaushik Roy, “A 32 kb l0T SubThreshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS,” IEEE J. of Solid-State Circuits, vol. 44, no.2, pp.650-658, Feb. 2009. [6]Evert Seevinck et al., “Static-noise margin analysis of MOS SRAM cells,” IEEE J. of Solid-State Circuits, vol. SC-22, no. 5, pp. 748–754, Oct. 1987. [7]Evelyn Grossar et al., “Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies,” IEEE J. of Solid-State Circuits, vol. 41, no. 11, pp. 2577–2588, Nov. 2006. [8]Ming-Hung Chang, Yi-Te Chiu, Shu-Lin Lai, and Wei Hwang, “A 1kb 9T Subthreshold SRAM with Bit-interleaving Scheme in 65nm CMOS,” International Symposium on Low Power Electronics and Design (ISLPED), pp. 291 - 296, 2011. [9]“Advantest V93000 PS1600 User Manual”, National Chip Implementation Center [10]Meng-Fan Chang, Shi-Wei Chang, Po-Wei Chou, and Wei-Cheng Wu, “A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications,” IEEE J. Solid-State Circuits, vol.46, no. 2, pp.520–529, Feb. 2011 [11]Bo Zhai, Scott Hanson, David Blaauw, and Dennis Sylvester, “A Variation-Tolerant Sub-200 mV 6-T Subthreshold SRAM,” IEEE J. Solid-State Circuits, vol. 43, no. 10, pp. 2338-2348, Oct. 2008 [12]Neil Weste and David Harris, CMOS VLSI Design: A Circuits and Systems Perspective (4th edition), Addison Weslay | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18171 | - |
| dc.description.abstract | 在本篇論文中，一個0.4伏特單次存取能量消耗4.76微微焦耳11.6百萬赫芝1千位元靜態隨機存取記憶體被實現，以台積電90奈米互補式金氧半製程製造完成。由於單端存取的機制，與傳統的6個電晶體記憶單元相比，所提出的7個電晶體記憶單元消耗較少功率。回授路徑切斷與讀取分離式技術，可使所提出的7個電晶體記憶單元擁有更好的寫入邊限與讀取雜訊邊限。為了達成製程、電壓以及溫度的變異容忍，在不損害總功率的情況下，以複製單一列記憶單元與複製單一行記憶單元來實現寫入與讀取偵測技術。測試晶片的量測結果顯示從1.0伏特到0.4伏特皆呈現低能量消耗，並且與後模擬結果相符。最後，採用這些技術後，實現了穩定且低能量消耗的靜態隨機存取記憶體，可以被使用在對能量有限制的應用中。 | zh_TW |
| dc.description.abstract | In this thesis, a 400mV 4.76pJ/Access 11.6MHz 1Kb SRAM is implemented in TSMC 90nm 1P9M CMOS process. Due to single-ended access, the proposed 7T SRAM cell consumes less power compared to the traditional 6T SRAM cell. With the feedback-loop-cutting scheme and the read-separated scheme, the proposed 7T SRAM cell possesses better write margin (WM) and read static noise margin (RSNM). To achieve PVT variation tolerance, the write and read detecting scheme is implemented by the single row repeat (SRR) circuit and the single column repeat (SCR) circuit without compromising the total power consumption. Measurement results of a test chip show that the proposed SRAM system consumes low energy from 1.0V to 0.4V, and agree with the post-simulation results. Finally, these schemes achieve the stable and low-energy consumption SRAM, which can be used in energy-constraint applications. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T00:53:32Z (GMT). No. of bitstreams: 1 ntu-104-R00943101-1.pdf: 3738108 bytes, checksum: 36ef4c93aa952e22b4af44eecd69f410 (MD5) Previous issue date: 2015 | en |
| dc.description.tableofcontents | 口試委員會審定書 i
誌謝 ii 中文摘要 iii Abstract iv Contents v List of Figures vii List of Tables x Chapter 1 Introduction to SRAM 1 1.1 SRAM Trends 1 1.2 Summary of Different Low-voltage SRAM Designs 9 Chapter 2 Proposed Single-ended 7T SRAM Bit Cell 11 2.1 The Analysis of Hold Static Noise Margin (HSNM) 13 2.2 The Analysis of Write Margin (WM) 16 2.3 The Analysis of Read Static Noise Margin (RSNM) 21 2.4 The Analysis of Access Delay Time 24 2.5 The Analysis of Access Power Consumption 32 Chapter 3 Proposed Low-Energy-Consuming SRAM 34 3.1 Introduction 34 3.2 Proposed SRAM Architecture 37 3.3 Read Pulse Generator with Read Detecting Scheme 40 3.4 Write Pulse Generator with Write Detecting Scheme 47 3.5 Latches 54 3.6 Address Decoder 56 Chapter 4 Simulation and Measurement Results 58 4.1 Post-simulation Waveforms 58 4.2 Post-simulation Results 60 4.3 Average Power Analysis for Sub-circuits 63 4.4 Layout Implementation 65 4.5 Summary of the post-simulation results 67 4.6 Experimental Results 68 4.6.1 Introduction 68 4.6.2 Measurement Environment Setup 68 4.6.3 PCB Layout 70 4.6.4 Measurement Results for the Maximum Frequency 72 4.6.5 Measurement Results for the Energy Consumption 77 4.7 Summary of the Measurement Results 79 4.8 Summary of Different Low-voltage SRAM Designs 80 Chapter 5 Conclusion and Future Work 81 REFERENCES 82 | |
| dc.language.iso | en | |
| dc.title | 一個0.4伏特單次存取能量消耗4.76微微焦耳11.6百萬赫芝1千位元靜態隨機存取記憶體具有提出的單端存取7個電晶體記憶單元並使用寫入與讀取偵測技術 | zh_TW |
| dc.title | A 400mV 4.76pJ/Access 11.6MHz 1Kb SRAM with Proposed Single-ended 7T Cell Using Write and Read Detecting Schemes | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 103-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.coadvisor | 陳中平(Charlie Chung-Ping Chen) | |
| dc.contributor.oralexamcommittee | 曹恆偉(Hen-Wai Tsao),黃威(Wei Hwang),廖宏仁(Hong-Ren Liao) | |
| dc.subject.keyword | 7個電晶體靜態隨機存取記憶單元,靜態隨機存取記憶體,低電壓,低功率,製程變異容忍, | zh_TW |
| dc.subject.keyword | 7T SRAM cell,SRAM,low-voltage,low-power,process variation tolerance, | en |
| dc.relation.page | 83 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2015-06-03 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-104-1.pdf 未授權公開取用 | 3.65 MB | Adobe PDF |
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