請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17841完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉致為(CheeWee Liu) | |
| dc.contributor.author | Der-Chuan Lai | en |
| dc.contributor.author | 賴德全 | zh_TW |
| dc.date.accessioned | 2021-06-08T00:44:30Z | - |
| dc.date.copyright | 2015-08-16 | |
| dc.date.issued | 2015 | |
| dc.date.submitted | 2015-08-06 | |
| dc.identifier.citation | [1] Moore, G.E., Cramming more components onto integrated circuits (Reprinted from Electronics, pg 114-117, April 19, 1965). Proceedings of the IEEE, 1998. 86(1): p.82-85
[2] C. Auth, C.A., A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarmane, T. Ghani, T. Glassman, R. Grover, W. Han, , et al. A 22nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, Self-Aligned Contacts and High Density MIM Capacitors in VLSI 2012. [3] Ionescu, A. M., De Michielis, L., Dagtekin, N., Salvatore, G., Cao, J., Rusu, A., & Bartsch, S. (2011, December). Ultra low power: Emerging devices and their benefits for integrated circuits. In Electron Devices Meeting (IEDM), 2011 IEEE International (pp. 16-1) [4] Kittel, Charles, Introduction to Solid State Physics, 7th Ed., Wiley, 1996 [5] Richard P Feynman, Robert B Leighton, Matthew L Sands, Feynman Lectures on Physics Complete Volumes 2, p.134 [6] Salvatore, G., Bouvet, D., & Ionescu, A. M. (2008, December). Demonstration of subthrehold swing smaller than 60mV/decade in Fe-FET with P (VDF-TrFE)/SiO 2 gate stack. In Electron Devices Meeting, 2008. IEEE International (pp. 1-4) [7] Rusu, A., Salvatore, G., Jimenez, D., & Ionescu, A. M. (2010, December). Metal-ferroelectric-meta-oxide-semiconductor field effect transistor with sub-60mV/decade subthreshold swing and internal voltage amplification. In Electron Devices Meeting (IEDM), 2010 IEEE International (pp. 16-3) [8] Lee, M. H., Lin, J. C., Wei, Y. T., Chen, C. W., Tu, W. H., Zhuang, H. K., & Tang, M. (2013, December). Ferroelectric negative capacitance hetero-tunnel field-effect-transistors with internal voltage amplification. In Electron Devices Meeting (IEDM), 2013 IEEE International (pp. 4-5) [9] Li, J., Nagaraj, B., Liang, H., Cao, W., Lee, C. H., & Ramesh, R. (2004). Ultrafast polarization switching in thin-film ferroelectrics. Applied physics letters, 84(7), 1174-1176. [10] Müller, J., Yurchuk, E., Schlösser, T., Paul, J., Hoffmann, R., Müller, S., ... & Mikolajick, T. (2012, June). Ferroelectricity in HfO 2 enables nonvolatile data storage in 28 nm HKMG. In VLSI Technology (VLSIT), 2012 Symposium on(pp. 25-26). IEEE. [11] J. F. Scotta, K. Watanabeab, A. J. Hartmannc & R. N. Lambc, Device models for PZT/PT, BST/PT, SBT/PT, and SBT/BI ferroelectric memories, Ferroelectrics Volume 225, Issue 1, 1999 [12] Nguyen, C. A., & Lee, P. S. (2005, December). Capacitance-voltage measurement in memory devices using ferroelectric polymer. In Microelectronics, MEMS, and Nanotechnology (pp. 60370S-60370S). International Society for Optics and Photonics. [13] Salahuddin, Sayeef, and Supriyo Datta. 'Use of negative capacitance to provide voltage amplification for low power nanoscale devices.' Nano letters8.2 (2008): 405-410. [14] Appleby, D. J., Ponon, N. K., Kwa, K. S., Zou, B., Petrov, P. K., Wang, T., ... & O’Neill, A. (2014). Experimental observation of negative capacitance in ferroelectrics at room temperature. Nano letters, 14(7), 3864-3868. [15] Haun, M. J., Furman, E., Jang, S. J., & Cross, L. E. (1989). Thermodynamic theory of the lead zirconate-titanate solid solution system, part I: phenomenology. Ferroelectrics, 99(1), 13-25. [16] Haun, M. J., Zhuang, Z. Q., Furman, E., Jang, S. J., & Cross, L. E. (1989). Thermodynamic theory of the lead zirconate-titanate solid solution system, part III: Curie constant and sixth-order polarization interaction dielectric stiffness coefficients. Ferroelectrics, 99(1), 45-54. [17] Physics of Ferroelectrics: A Modern Perspective, Topics in Applied Physics, edited by K. Rabe, C. H. Ahn, and J.-M. Triscone (Springer, Berlin, 2007), Vol. 105. [18] Landau, L. D.; Khalatnikov, I. M. On the anomalous absorption of sound near a second order phase transition point. Dokl. Akad. Nauk 1954, 96, 469-472 [19] Lo, V. C. Simulation of thickness effect in thin ferroelectric films using Landau-Khalatnikov theory. J. Appl. Phys. 2003, 93 (5), 3353- 3359 [20] Zhang, W.; Bhattacharya, K. A computational model of ferroelectric domains. Part I: model formulation and domain switching. Acta Mater. 2005, 53, 185-198 [21] Taur, Yuan, and Tak H. Ning. Fundamentals of modern VLSI devices. Cambridge university press, 2009. [22] Colinge, J.P., Multi-gate SOI MOSFETs. Microelectronic Engineering, 2007. 84(9-10): p. 2071 [23] Y. Taur, “Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs,” IEEE Trans. Electron Devices, vol. 48, pp. 2861–2869, Dec. 2001. [24] Fowkes, Frederick M. and Hess, Dennis W., Control of fixed charge at Si-Si02 interface by oxidation-reduction Treatments, Applied Physics Letters, 22, 377-379 ,1973 [25] Dingemans, G., Terlinden, N. M., Verheijen, M. A., Van de Sanden, M. C. M., & Kessels, W. M. M. (2011). Controlling the fixed charge and passivation properties of Si (100)/Al2O3 interfaces using ultrathin SiO2 interlayers synthesized by atomic layer deposition. Journal of Applied Physics, 110(9), 093715. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17841 | - |
| dc.description.abstract | 隨著摩爾定律持續將元件微縮化，降低邏輯元件的操作功率是必要的；縮小元件的操作電壓為達成此目的的有效手段。在不降低元件的導通啟動電流與不提升漏電流的前提下，欲降低元件的操作電壓，須縮小元件的次臨界斜率。然而傳統電晶體在次臨界斜率上有最小極值的限制，即使將元件次臨界斜率減低至此極值，仍不足以滿足未來更小尺度元件微縮對次臨界斜率的要求；因此，陡峭次臨界斜率元件的研究，即為當前重要的研究議題。
鐵電層負電容電晶體為近期提出的新穎陡峭次臨界斜率元件，其它陡峭次臨界斜率元件像是穿隧式場效電晶體、奈米微機電元件及衝擊游離式場效電晶體，皆分別面臨操作電流過低、反應時間過長以及操作電壓過大與可靠度的問題。傳統鐵電層負電容電晶體的不足之處，在於追求陡峭次臨界斜率時可能產生電流曲線的遲滯效應。 本論文中，我們探討鐵電層負電容的成因與它對元件電性的影響，建立鐵電層負電容電晶體的電性模擬，並提出二個新型鐵電層負電容電晶體結構，以改善傳統負電容電晶體追求陡峭次臨界斜率時出現電流遲滯曲線的缺點。 | zh_TW |
| dc.description.abstract | Transistor scaling down has been the principal factor in driving CMOSFET performance improvement for more than thirty years. As transistor scales down, reduction of dynamic switching power (fCVDD2) is required, in concern of power consumption and heat dissipation issue. Transistor operating frequency and capacitance cannot be lowered, in pursuit of higher speed and on current. Therefore, lowering Vdd is the solution to reduce the dynamic switching power as technology nodes progress.
In transistor design, IOFF should remain the same or become even lower to maintain low static power (IOFFVDD), and ION shouldn’t be lower for the sake of delay. As a result, devices with steep subthreshold slopes are desired. However, traditional transistor subthreshold slope is limited at 60 mV/decade due to its thermionic emission transport mechanism. To break through the limit, steep-slope devices with subthreshold slope smaller than 60 mV/decade are required. Candidates of steep-slope devices include Negative Capacitance FET (NCFET), Tunneling FET (TFET), Nanoelectromechanical relay (NEM relay), and Impact-ionization MOS (IMOS). While TFET suffers from low on current, IMOS suffers from high operating voltage and reliability issue due to its breakdown transport mechanism, and NEM relay suffers from large hysteresis loop and low speed on switching. NCFET stands to be the promising steep-slope device among the candidates. Though traditional NCFET may have hysteresis loop in seek of steep SS, the hysteresis loop can still be eliminated by some novel structure designs of NCFET proposed in the thesis. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T00:44:30Z (GMT). No. of bitstreams: 1 ntu-104-R02943058-1.pdf: 2058767 bytes, checksum: 6ab02535f2048ae787d3a1dca3cb6f43 (MD5) Previous issue date: 2015 | en |
| dc.description.tableofcontents | Related Publication i
中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vi LIST OF TABLES x Chapter 1 Introduction 1 1.1 Why Steep-Slope Devices? 1 1.2 Steep-Slope Device: Ferroelectric Negative Capacitance FET 3 1.3 Progress on Ferroelectric Negative Capacitance FET 6 Chapter 2 Physics and Simulation Methodology of Ferroelectric Negative Capacitance (NC) 9 2.1 Ferroelectric Negative Capacitance(NC) 9 2.1.1 Physic Origins of Negative Capacitance 9 2.1.2 Experimental Evidence of Negative Capacitance 12 2.2 Landau Theory of Ferroelectric 13 2.2.1 Gibbs free energy of Ferroelectric 13 2.2.2 Ferroelectric hysteresis and stabilization 16 2.2.3 Behavior of Ferroelectric with series capacitance 20 2.3 Simulation methodology of Ferroelectric Negative Capacitance FET 25 2.4 Summary 26 Chapter 3 Simulation Analysis of Ferroelectric Negative Capacitance FET 28 3.1 Design rules of Ferroelectric Negative Capacitance FET 28 3.2 Simulation of Ferroelectric Negative Capacitance FET 31 3.3 NCFET operation with hysteresis 33 3.3.1 Simulation of NCFET with hysteresis 33 3.3.2 Reduction of Hysteresis by Fixed Charge 40 3.4 NCFET Performance Tuning 42 3.4.1 Effects of Overlap Capacitance and Gate Length Scaling 42 3.4.2 Effect of Drain Voltage 46 3.4.3 Effect of Oxide EOT 47 3.4.4 Effect of Channel Doping 48 3.5 Summary 49 Chapter 4 Optimized NC Gate Structures to Achieve Hysteresis-Free Ferroelectric NCFETs 50 4.1 Simulation of Double-Gate NCFET 50 4.2 Ferroelectric NCFETs using Charged Gate Oxide 53 4.3 Simulation of Ferroelectric NCFETs using Charged Gate Oxide 56 4.4 Ferroelectric NCFETs using Polysilicon Gate stack 57 4.5 Simulation of Ferroelectric NCFETs using Polysilicon Gate stack 59 4.6 Summary 61 Chapter 5 Conclusion and Future Work 62 5.1 Conclusion 62 5.2 Future direction 64 REFERENCE 65 | |
| dc.language.iso | zh-TW | |
| dc.title | 鐵電層負電容場效電晶體之模擬與特性分析 | zh_TW |
| dc.title | Simulation and Electrical Characteristics of Ferroelectric
Negative Capacitance Field Effect Transistors | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 103-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 張顏暉,林中一,林吉聰 | |
| dc.subject.keyword | 鐵電層,負電容,次臨界斜率,遲滯曲線, | zh_TW |
| dc.subject.keyword | ferroelectric material,negative capacitance,subthreshold slope,hysteresis, | en |
| dc.relation.page | 68 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2015-08-06 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-104-1.pdf 未授權公開取用 | 2.01 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。