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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 楊宏智 | |
| dc.contributor.author | Chao-Wei Tang | en |
| dc.contributor.author | 唐肇蔚 | zh_TW |
| dc.date.accessioned | 2021-06-08T00:31:28Z | - |
| dc.date.copyright | 2013-07-25 | |
| dc.date.issued | 2013 | |
| dc.date.submitted | 2013-07-02 | |
| dc.identifier.citation | [1] C. DeMilo., C. Bergad., R. Forni., T. Brukilacchio., Thermally induced stresses resulting from coefficient of thermal expansion differentials between an LED sub-mount material and various mounting substrates, Proceedings of SPIE, 6486, pp. 64860–64869. (2007).
[2] X. Fan., Wafer level system packaging and integration for solid state lighting (SSL), 13th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, pp. 1–6. (2012). [3] M. Arik., C. Becker., S. Weaver., J. Petroski., Thermal management of LEDs: package to system, Proceedings of SPIE, 5187, pp. 64–75. (2004). [4] M.Y. Tsai., Thermal resistance and reliability of high-power LED packages under WHTOL and thermal shock tests, IEEE Transactions on Components and Packaging Technologies, 33(4), pp. 738–746. (2010). [5] J. Lau., R. Lee., M. Yuen., P. Chan., 3D LED and IC wafer level packaging, Microelectronics International, 27(2), pp. 98–105. (2010). [6] Y. Developpment., 3D integration ifrastructure & market Status, Semicon Taiwan, pp. 1–35. (2010). [7] S.W.R. Lee., Advanced LED wafer level packaging technologies, International Microsystems, Packaging, Assembly, and Circuits Technology Conference, pp. 71–74. (2011). [8] T. Uhrmann., T. Matthias., P. Lindner., Silicon-based wafer-level packaging for cost reduction of high brightness LEDs, Electronic Components and Technology Conference, pp. 1622–1625. (2011). [9] S.K. Ryu., Thermal-mechanical stress analysis and interfacial reliability for through-silicon-vias in three dimensional interconnect structures, Doctorial Dissertation of the University of Texas at Austin, pp. 1–124. (2011). [10] R.R. Schaller., Moore's law: past, present and future, IEEE Spectrum, 34(6), pp. 52–59. (1997). [11] B. Li., T.D. Sullivan., T.C. Lee., D. Badami., Reliability challenges for copper interconnects, Microelectronics Reliability, 44(3), pp. 365–380. (2004). [12] M.T. Bohr., Interconnect scaling-the real limiter to high performance ULSI, International Electron Devices Meeting, pp. 241–244. (1995). [13] Y.J. Ma., H.N. Yang., J. Guo., C. Sathe., A. Agui., J. Nordgren., Structural and electronic properties of low dielectric constant fluorinated amorphous carbon films, Applied Physics Letters, 72(25), pp. 3353–3355. (1998). [14] H. Treichel., G. Ruhl., P. Ansmann., R. Wurl., C. Muller., M. Dietlmeier., Low dielectric constant materials for interlayer dielectric, Microelectronic Engineering, 40(1), pp. 1–19. (1998). [15] H. Zhou., F.G. Shi., B. Zhao., J. Yota., Effect of deposition methods on dielectric breakdown strength of PECVD low-k carbon doped silicon dioxide dielectric thin films, Microelectronics Journal, 35(7), pp. 571–576. (2004). [16] G. Bomchil., A. Halimaoui., R. Herino., Porous silicon: The material and its applications in silicon-on-insulator technologies, Applied Surface Science, 41-42(0), pp. 604–613. (1989). [17] R. Yarema1., The via revolution, Proceedings of Science, pp. 1–11, 2010. [18] M. Motoyoshi., Through-silicon via (TSV), Proceedings of the IEEE, 97, pp. 43–48. (2009). [19] M. Koyanagi., T. Fukushima., T. Tanaka., High-density through silicon vias for 3D LSIs, Proceedings of the IEEE, 97, pp. 49–59. (2009). [20] V. Sundaram., Q. Chen., Y. Suzuki., G. Kumar., F. Liu., R. Tummala., Low-cost and low-loss 3d silicon interposer for high bandwidth logic-to-memory interconnections without TSV in the logic IC, 62th Electronic Components and Technology Conference, pp. 292–297. (2012). [21] W. Y. Seung., Q. Zhou., K. Pasad., V. Kripesh., J.H. Lau., High RF performance TSV silicon carrier for high frequency application, 58th Electronic Components and Technology Conference, pp. 1946 – 1952. (2008). [22] D. Tezcan., F. Duval., H. Philipsen., Q. Luhn., P. Soussan., B. Swinnen., Scalable through silicon via with polymer deep trench isolation for 3d wafer level packaging, 59th Electronic Components and Technology Conf. pp. 1159–1164. (2009). [23] Y. Civale., D. Tezcan., H. Philipsen., F. Duval., P. Jaenen., Y. Travaly., P. Soussan., B. Swinnen., E. Beyne., 3-D Wafer-level packaging die stacking using spin-on-dielectric polymer liner through-silicon vias, IEEE Transaction Component Package Manufacturing Technology, pp. 1833–1840. (2011). [24] M. Rimskog., Through Wafer Via Technology for MEMS and 3D Integration, Electronics Manufacturing Technology Symposium, pp. 286–289. (2007). [25] C.D. Gu., H. Xu., T.Y. Zhang., Fabrication of high aspect ratio through-wafer copper interconnects by reverse pulse electroplating, Journal of Micromechanics and Microengineering, 19(065011), pp. 1–5. (2009). [26] Y.K. Ko., H.T. Fujii., Y.S. Sato, C.W. Lee., S. Yoo., High-speed TSV filling with molten solder, Microelectronics Engineering, 89, pp. 62–64. (2012). [27] J. Gu., W. Pike., W. Karl., A novel capillary-effect-based solder pump structure and its potential application for through-wafer interconnection, Journal of Micromechanics and Microengineering, 19(074005), pp. 1–7. (2009). [28] N. Jackson., J. Muthuswamy., Flexible chip-scale package and interconnect for implantable MEMS movable microelectrodes for the brain, Journal of Microelectromechanics System, 18, pp. 396–404. (2009). [29] J. Yuan., W.K. Jeung., C.H. Lim., S.W. Park., Y.D. Kweon., S. Yi., A low-cost through via interconnection for ISM WLP, Microsystems Technolology, 15, pp. 1273–1277. (2009). [30] A.C. Fischer., S.J. Bleiker., T. Haraldsson., N. Roxhed., G. Stemme., F. Niklaus., Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic assembly of nickel wires, Journal of Micromechanics and Microengineering, 22(105001) pp. 1–9. (2012). [31] Y.H. Lee., K.J. Choi., Analysis of silicon via hole drilling for wafer level chip stacking by UV laser, International Journal of Precision Engineering Manufacturing, 11, pp. 501–507. (2010). [32] A.C. Fischer., S.J. Bleiker., T. Haraldsson., N. Roxhed., G. Stemme., F. Niklaus., Wire-bonded through-silicon vias with low capacitive substrate coupling, Journal of Micromechanics and Microengineering, 21(085035), pp. 1–8. (2011). [33] Y.H. Chen., W.C. Lo., T.Y. Kuo., Thermal Effect Characterization of Laser-Ablated Silicon-Through Interconnect, Electronics System integration Technology Conference, pp. 594–599. (2006). [34] C.W. Tang., H.T. Young., K.M. Li., Innovative through-silicon-via formation approach for wafer-level packaging applications, Journal of Micromechanics and Microengineering, 22(045019), pp. 1–8. (2012). [35] M. Kawano., N. Takahashi., Y. Kurita., K. Soejima., M. Komuro., S. Matsui., Three-dimensional packaging technology for stacked DRAM with 3-Gb/s data transfer, IEEE Transactions on Electron Devices, 55(7), pp. 1614–1620. (2008). [36] R. Nagarajan., K. Prasad., L. Ebin., B. Narayanan., Development of dual-etch via tapering process for through-silicon interconnection, Sensors and Actuators A, 139, pp. 323–329. (2007). [37] H.V. Jansen., M.J.d. Boer., S. Unnikrishnan., M.C. Louwerse., M.C. lwenspoek., Black silicon method X: a review on high speed and selective plasma etching of silicon with profile control: an in-depth comparison between Bosch and cryostat DRIE processes as a roadmap to next generation equipment, Journal of Micromechanics and Microengineering, 19(033001), pp.1–41. (2009). [38] B. Wu., A. Kumar., S. Pamarthy., High aspect ratio silicon etch: A review, Journal of Applied Physics, 108(051101), pp. 1–20. (2010). [39] X. Wang., W. Zeng., G. Lu., O.L. Russo., E. Eisenbraun., High aspect ratio Bosch etching of sub-0.25μ trenches for hyper integration applications, Journal of Vacuum Science Technology B, 25(13), pp. 76–81. (2007). [40] C.L. Chang., Y.F. Wang., Y. Kanamori., J.J. Shih., Y. Kawai., C.K. Lee., K.C. Wu., M. Esashi., Etching submicrometer trenches by using the Bosch process and its application to the fabrication of antireflection structures, Journal of Micromechanics and Microengineering, 15 pp. 580–585. (2005). [41] Y.H. Ham., D.P. Kim., K.S. Park., Y.S. Jeong., H.J. Yun., K.H. Baek., K.H. Kwon, K. Lee., L.M. Do, Dual etch processes of via and metal paste filling for through silicon via process, Thin Solid Films, 519, pp. 6727–6731. (2011). [42] B. Tan., K. Venkatakrishnan., Nd-YAG laser microvia drilling for interconnection application, Journal of Micromechanics and Microengineering, 17, pp. 1511–1517. (2007). [43] K. Venkatakrishnan., B. Tan., Interconnect microvia drilling with a radially polarized laser beam, Journal of Micromechanics and Microengineering, 16, pp. 2603–2607. (2006). [44] B. Tan., Deep micro hole drilling in a silicon substrate using multi-bursts of nanosecond UV laser pulses, Journal of Micromechanics and Microengineering, 16, pp. 109–112. (2006). [45] C.W. Lin., H.A. Yang., W.C. Wang., W.L. Fang., Implementation of three-dimensional SOI-MEMS wafer-level packaging using through-wafer interconnections, Journal of Micromechanics and Microengineering, 17, pp. 1200–1205. (2007). [46] Kruger., G. Schone., T. Wernicke., W. John., J. Wurfl., G. Trankle., UV laser drilling of SiC for semiconductor device fabrication, Journal of Physics Conference, 59, pp. 740–744. (2007). [47] H. Panster., H. Herfurth., S. Heinemann., P. Laakso., R. Penttila., Y. Liu., G. Newaz., Laser microvia drilling and ablation of silicon using 355 nm pico and nanosecond pulses, Laser Microprocessing Conference, pp. 278–287. (2008). [48] M. Steinert., J. Acker., M. Krause., S. Oswald., K. Wetzig., Reactive species generated during wet chemical etching of silicon in HF/HNO3 mixtures, Journal of Physics Chemistry B, 110, pp. 11377–11382. (2006). [49] M. Steinert., J. Acker., A., Henßge., K. Wetzig., Experimental studies on the mechanism of wet chemical etching of silicon in HF/HNO3 mixtures, Journal of Electrochemical Society, 152, pp. 843–850. (2005). [50] H. Robbins., B. Schwartz., Chemical etching of silicon I: the system of HF, HNO3, and H2O, Journal of Electrochemical Society, 106, pp. 505–508. (1959). [51] H. Robbins., B. Schwartz., Chemical etching of silicon II: the system HF, HNO3, H2O, and HC2H3O, Journal of Electrochemical Society, 107, pp. 108–111. (1960). [52] B. Schwartz., H. Robbins., Chemical etching of silicon III: a temperature study in the acid system, Journal of Electrochemical Society, 108, pp. 365–372. (1961). [53] J.Z. Hu., L.Q. Yang., M.W. Shin., Thermal and mechanical analysis of high-power LEDs with ceramic packages, IEEE Transactions on Device and Materials Reliability, 8(2), pp. 297–303 (2008). [54] S. Gupta., M. Hilbert., S. Hong., R. Patti., Techniques for producing 3D ICs with high-density interconnect, Tezzaron Semiconductor Corporation, pp. 1. (2003). [55] Micronews., Silicon WLP modules may be next step for Taiwan’s HB-LED Packagers, Advanced Packaging, http://www.i-micronews.com. (2009). [56] J. Dukovic., TSV integration at applied, ITRI Workshop on 3DIC TSV & Thin Wafer Handling, pp. 1–17. (2010). [57] M.W. Pruessner., W.S. Rabinovich., T.H. Stievater., D. Park., J.W. Baldwin., Cryogenic etch process development for profile control of high aspect-ratio submicron silicon trenches, Journal of Vacuum Science Technology B, 25, pp. 21–28. (2007). [58] L.A. Donohue., J. Hopkins., R. Barnett., A. Newton., A. Barker., Developments in Si and SiO2 Etching for MEMS based optical applications, Proceedings of SPIE, 5347, pp. 44–53. (2004). [59] H.C. Liu., Y.H. Lin., W. Hsu., Sidewall roughness control in advanced silicon etch process, Microsystem Technologies, 10, pp. 29–34. (2003). [60] T. Defforge., X. Song., G. Gautier., T. Tillocher., R. Dussart., S. Kouassi., T.V. Francois., Scalloping removal on DRIE via using low concentrated alkaline solutions at low temperature, Sensor Actuators A, 170, 114–120. (2011). [61] S. Tanaka., K. Sonoda., K. Kasai., K. Kanda., T. Fujita., K. Higuchi., K. Maenaka, Crystal orientation dependent etching in RIE and its application, MEMS conference 978-1-4244-9634-1, pp. 217–220. (2011). [62] Y.C. Hsin., C.C. Chen., J.H. Lau., P.J. Tzeng., S.H. Shen.,Y.F. Hsu., S.C. Chen., C.Y. Wn., J.C. Chen., T.K. Ku., M.J. Kao., Effects of etch rate on scallop of through-silicon vias (TSVs) in 200mm and 300mm wafers, Electronic Components and Technology Conference, pp. 1130–1135. (2011). [63] T. Dave., TSV formation technologies for 3D-IC, SPTS, pp. 1–41. (2010). [64] K.E. Bean., Anisotropic etching of silicon, IEEE Transactions on Electron Devices, 25(10), pp. 1186–1193. (1978). [65] H.T. Young., C.C. Lin., H.T. Liao., Precision wafer thinning and its surface conditioning technique, International Journal of Materials and Product Technology, 31(1), pp. 36–45. (2008). [66] N. Tosun., Determination of optimum parameters for multi-performance characteristics in drilling by using grey relational analysis, International Journal of Advanced Manufacturing Technology, 28, pp. 450–455. (2006). [67] R.S. Pawade., S.S. Joshi., Multi-objective optimization of surface roughness and cutting forces in high-speed turning of Inconel 718 using Taguchi grey relational analysis (TGRA), International Journal of Advanced Manufacturing Technology, 56, pp. 47–62. (2011). [68] C.J. Tzeng., Y.H. Lin., Y.K. Yang., M.C. Jeng., Optimization of turning operations with multiple performance characteristics using the Taguchi method and Grey relational analysis, Journal of materials processing technology, 209, pp. 2753–2759. (2009). [69] J. Kopac., P. Krajnik., Robust design of flank milling parameters based on grey-Taguchi method, Journal of Materials Processing Technology, 191, pp. 400–403. (2007). [70] Y.S. Tarng., S.C. Juang., C.H. Chang., The use of grey-based Taguchi methods to determine submerged arc welding process parameters in hardfacing, Journal of Materials Processing Technology, 128, pp. 1–6. (2002). [71] H. Nurhadi., Y.S. Tarng., Experimental approached optimisation of a linear motion performance with grey hazy set and Taguchi analysis methods (GHST) for ball-screw table type, International Journal of Advanced Manufacturing Technology, 44(1–2), pp. 149–160. (2009). [72] S. Manivannan., S. P. Devi., R. Arumugam., N.M. Sudharsan., Multi-objective optimization of flat plate heat sink using Taguchi-based Grey relational analysis, International Journal of Advanced Manufacturing Technology, 52, pp. 739–749. (2011). [73] J. Z. Hu., L.Q. Yang., W.J. Hwang., M.W. Shin., Thermal and mechanical analysis of delamination in GaN-based light-emitting diode packages, Journal of Crystal Growth, 288, pp. 157–161, (2006). [74] C.P. Wang., T.T. Chen., H.K. Fu., T.L. Chang., P.T. Chou., M.T. Chu., Analysis of thermal characteristics and mechanism of degradation of flip-chip high power LEDs, Microelectronics Reliability, 52, pp. 698–703. (2012). [75] J.Z. Hu., L.Q. Yang., M.W. Shin., Mechanism and thermal effect of delamination in light-emitting diode packages, Microelectronics Journal, 38, pp. 157–163. (2007). [76] J.F. Verweij., J.H. Klootwijk., Dielectric breakdown I: A review of oxide breakdown, Microelectronics Journal, 27, pp. 611–622. (1996). [77] Q. Zhou., H.W. Chen., C.H. Zhou., Z.H. Feng., S.J. Cai., K.J. Chen., Schottky source/drain InAlN/AlN/GaN mishemt with enhanced breakdown voltage, IEEE Electron Device Letters, 33(1), pp. 38–40. (2012). [78] M. Esashi., Wafer level packaging of MEMS, Journal of Micromechanics and Microengineering, 18(073001), pp. 1–13. (2008). [79] N. Khan., V.S. Rao., S. Lim., H.S. Wee., V. Lee., X. Zhang., E.B. Liao., R. Nagarajan., T.C. Chai., V. Kripesh., J.H. Lau., Development of 3-D silicon module with TSV for system in packaging, IEEE Transaction Component Package Technology, 33, pp. 3–8. (2010). [80] B. Eaton., TSV etch seminar, ITRI TSV Seminar, pp. 1–30. (2010). [81] Cree., XLamp LEDs electrical overstress, Cree, pp. 1–9. (2010). [82] W.H. Juan., S.W. Pang., Controlling sidewall smoothness for micromachined Si mirrors and lenses, Journal of Vacuum Science and Technology B, 14(6), pp. 4080–4084. (1996). [83] N. Narendran., Y. Gu., Life of LED-based white light sources, Display Technology, Journal of, 1(1), pp. 167–171. (2005). [84] J. Park., C.C. Lee., An electrical model with junction temperature for light-emitting diodes and the impact on conversion efficiency, IEEE Electron Device Letters, 26(5), pp. 308–310. (2005). [85] D. Pinjala., M.K. Iyer., S.G. Chow., I.J. Rasiah., Thermal characterization of vias using compact models, Electronics Packaging Technology Conference, pp. 144–147. (2000). [86] 曾仕杰，「晶圓級矽導通孔基板製作分析與應用」，國立台灣大學碩士論文，2012。 [87] H.R. Shanks., P.D. Maycock., P.H. Sidles., G.C. Danielson., Thermal Conductivity of Silicon from 300 to 1400°K, Physical Review, 130(5), pp. 1743–1748. (1963). [88] W.H. Gitzen., Alumina as a ceramic material, Springer Publishing, pp. 1–264. (1970). [89] G. Pezzotti., I. Kamada., S. Miki., Thermal conductivity of AlN/polystyrene interpenetrating networks, Journal of the European Ceramic Society, 20(8), pp. 1197–1203. (2000). [90] W. Werdecker., F. Aldinger, Aluminum nitride-an alternative ceramic substrate for high power applications in microcircuits, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 7(4), pp. 399–404. (1984). [91] N. Kuramoto., H. Taniguchi., I. Aso., Translucent A1N Ceramic Substrate, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 9(4), pp. 386–390. (1986). [92] C. Osburn., D. Ormond., Dielectric breakdown in silicon dioxide films on silicon, Journal of the Electrochemical Society, 119(5), pp. 597–603. (1972). | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17694 | - |
| dc.description.abstract | 矽晶穿孔（TSV）製程為三維積體電路、系統級封裝、晶圓級封裝（WLP）等三維堆疊封裝科技之核心關鍵技術，近年來採用矽晶穿孔技術進行三維堆疊封裝儼然已成為封裝業者發展之主要趨勢。探索技術現況，深反應性離子蝕刻（DRIE）製程小從數微米直至數百微米以上尺寸之矽晶穿孔製作皆能勝任，是目前最廣為半導體業者所採用之矽晶穿孔製程方法。然而，深反應性離子蝕刻製程設備相當昂貴，無形中限制了此蝕刻工藝之應用層面。本論文有兩大研究重點，首先係創新矽晶穿孔製程之研發；接續為創新矽晶穿孔製程導入發光二極體封裝基板（LED sub-mount）應用之分析與驗證。本研究使用灰關聯田口（Grey-Taguchi）方法尋找濕式蝕刻製程之多品質最佳參數，藉由最佳化蝕刻製程移除奈秒雷射製程產生之矽晶缺陷。應用上針對發光二極體封裝基板之散熱性能、基板絕緣電性、高溫可靠度等關鍵特性進行分析與探討。實驗結果顯示灰關聯田口方法可確實找到區域多重品質最佳化參數並有效移除雷射加工產生之矽晶缺陷；採用矽晶穿孔基板作為發光二極體封裝基板能得到較氧化鋁基板優異之散熱性能；創新矽晶穿孔製程導入發光二極體封裝基板應用相較於採奈秒雷射製程製作之基板能提昇623 %之崩潰電壓；晶圓級發光二極體封裝基板具備優異之高溫可靠度特性。本文提出之創新矽晶穿孔製程具備有，較低加工成本、高加工效率、優異加工品質等適合半導體相關業者將製程導入量產之關鍵特性。而晶圓級發光二極體封裝基板之關鍵特性與可靠度結果闡述了晶圓級發光二極體封裝基板取代陶瓷封裝基板之潛在機會。 | zh_TW |
| dc.description.abstract | Through-silicon via (TSV) is an emerging technology for three-dimensional integrated circuit, system-in-packaging, and wafer-level packaging (WLP) applications. Among several available TSV formation methods, Bosch deep reactive ion etching (DRIE) is widely used because it enables the fabrication of TSVs with almost any diameter, from the submicrometer level to hundreds of micrometers. However, the high cost of Bosch DRIE makes it uneconomical for industrial production. This dissertation is commenced with the development of innovative TSV formation approach, and then, the feasibility of the proposed new drilling strategy adopted in a practical light-emitting-diode (LED) sub-mount application is demonstrated. Here, an effective method for the optimization of multiple performance characteristics of wet chemical etching process to remove TSV defects based on Grey-Taguchi method is introduced. In the LED sub-mount application study, the thermal dissipation performance, dielectric breakdown voltage based on 1-μm-thick silicon dioxide dielectric layer, and the high-temperature reliability of silicon LED sub-mount are investigated. Experimental results confirm the efficacy of the multiple performance optimization method based on Grey-Taguchi method as well as demonstrating that the combined approach effectively eliminates the unwanted material formed by nanosecond (ns) laser pulses. The results also reveal that the silicon LED sub-mount shows superior thermal dissipation performance, the proposed innovative TSV formation approach represents an improvement of 623 % dielectric breakdown voltage over conventional ns laser drilling method with the same oxidation process condition, and the WLP LED sub-mount contains well high-temperature reliability feature. As a result, the proposed new TSV formation approach affords superior TSV quality, higher TSV throughput, and lower processing cost than Bosch DRIE. These advantages could provide the necessary impetus for rapid commercialization of the several high-density fabrication methodologies that depend on TSVs. Through this work, it has been demonstrated that with the proposed new approach, it is feasible to achieve a cost-effective silicon LED sub-mount for replacing the conventional ceramic sub-mounts in high brightness LED package application. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T00:31:28Z (GMT). No. of bitstreams: 1 ntu-102-D96522002-1.pdf: 13438567 bytes, checksum: d3ccc6d17e3f2f3a9ef793f4ad818e01 (MD5) Previous issue date: 2013 | en |
| dc.description.tableofcontents | 口試委員審定書 I
致謝 II 摘要 III Abstract IV Contents VI List of Figures XI List of Tables XVII Chapter 1 INTRODUCTION 1 1.1 Background 1 1.2 Motivation and objectives 2 1.3 Scope of dissertation 5 Chapter 2 LITERATURE REVIEW 7 2.1 3D stacked applications with TSVs 8 2.2 WLP LED sub-mount with TSVs 9 2.3 Process flow for TSV fabrication 10 2.3.1 TSV formation 11 2.3.1.1 Bosch deep reactive ion etching 12 2.3.1.2 Anisotropic WCE 14 2.3.1.3 Laser drilling 15 2.3.1.4 Isotropic WCE 19 2.4 Grey-Taguchi method 22 2.5 Reliability studies of LED sub-mount 25 2.5.1 Thermal management and mechanical analysis of LED packages 26 2.5.1.1 Fundamental heat transfer 26 2.5.1.2 Thermal resistance circuit method 27 2.5.1.3 Thermal and mechanical analysis 29 2.5.2 Dielectric breakdown field evaluation 31 Chapter 3 OPTIMIZATION OF WCE PARAMETERS WITH GREY-TAGUCHI METHOD 32 3.1 Introduction 33 3.2 Experimental works 35 3.2.1 Laser drilling with ns green laser pulses 35 3.2.2 WCE parameters setup 36 3.3 Grey relational analysis 38 3.4 Results and discussion 40 3.4.1 Confirmation test 46 3.5 Summary 47 Chapter 4 INNOVATIVE TSV FORMATION APPROACH FOR WLP APPLICATIONS 48 4.1 Introduction 49 4.2 Experimental setup 52 4.2.1 Designed pattern layout 52 4.2.2 Laser drilling with ns UV laser pulses 52 4.2.3 Laser drilling with ns green laser pulses 53 4.2.4 WCE 54 4. 3 Results and discussion 56 4. 3.1 Research on green ns laser pulses with optimized WCE process 56 4.3.1.1 Green ns laser drilled TSVs 56 4.3.1.2 Optimization of WCE etchant 57 4.3.1.3 WCE for debris and recast layer removing 59 4.3.1.4 Comparison of the green ns laser pulses with WCE approach and the Bosch DRIE method 60 4.3.2 Research on UV ns laser pulses with optimized WCE process 63 4.3.2.1 UV ns laser drilled TSVs 63 4.3.2.2 WCE process for HAZ, recast layer, and debris removal with a HF, HNO3, and PSI surfactant etchant 65 4.3.2.3 Comparison of the UV ns laser pulses with WCE approach and the Bosch DRIE method 68 4.3.2.4 Patent portfolio for innovative TSV formation approach 71 4.4 Summary 71 Chapter 5 ENHANCEMENT OF DIELECTRIC BREAKDOWN FIELD OF WLP LED SUB-MOUNT WITH THE INNOVATIVE TSV PROCESS 73 5.1 Introduction 73 5.2 Experimental setup 75 5.2.1 Designed pattern layout 76 5.2.2 Fabrication process flow of silicon LED sub-mount 77 5.2.3 Test method for evaluating dielectric breakdown field 78 5.3 Results and discussion 79 5.3.1 TSV formation 81 5.3.2 TSV isolation 85 5.3.3 Silicon LED sub-mount patterning 87 5.3.4 Dielectric breakdown field evaluation for silicon LED sub-mounts 89 5.4 Summary 92 Chapter 6 ANALYSIS OF THERMAL, ELECTRICAL, AND RELIABILITY PROPERTIES OF WLP LED SUB-MOUNT 94 6.1 Introduction 95 6.2 Fabrication process of WLP LED sub-mount 97 6.3 Experimental setup for thermal dissipation and insulation performances examination 98 6.3.1 Thermal dissipation performance examination 98 6.3.2 Insulation performance examination 100 6.4 High temperature reliability examination 101 6.4.3 TSV resistance examination 102 6.4.2 Metal peeling examination 103 6.5 Results and discussion 104 6.5.1 Analysis of thermal dissipation performance 104 6.5.2 Analysis of insulation performance 105 6.5.2.1 Breakdown voltage examination 106 6.5.2.2 Insulation resistance examination 107 6.5.3 High temperature reliability examination 109 6.5.3.1 TSV resistance examination 109 6.5.3.2 Metal peeling examination 109 6.6 Summary 110 Chapter 7 CONCLUSIONS AND FUTURE WORKS 112 7.1 Conclusions 112 7.2 Future works 114 REFERENCES 117 | |
| dc.language.iso | en | |
| dc.title | 開創性矽晶穿孔製程導入晶圓級發光二極體封裝基板之研究 | zh_TW |
| dc.title | Innovative Through-Silicon Via Formation Approach for Wafer-Level Packaging Light-Emitting-Diode Sub-mount Application | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 101-2 | |
| dc.description.degree | 博士 | |
| dc.contributor.oralexamcommittee | 黃聖杰,施文彬,李貫銘,張復瑜,楊敏聰 | |
| dc.subject.keyword | 矽晶穿孔,晶圓級封裝,深反應性離子蝕刻,發光二極體封裝基板,灰關聯田口方法, | zh_TW |
| dc.subject.keyword | Through-silicon via (TSV),Wafer-level packaging (WLP),Deep reactive ion etching (DRIE),Light-emitting-diode (LED) sub-mount,Grey-Taguchi method, | en |
| dc.relation.page | 127 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2013-07-02 | |
| dc.contributor.author-college | 工學院 | zh_TW |
| dc.contributor.author-dept | 機械工程學研究所 | zh_TW |
| 顯示於系所單位： | 機械工程學系 | |
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