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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17459完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳怡然 | |
| dc.contributor.author | Yu-Chiun Chen | en |
| dc.contributor.author | 陳玉群 | zh_TW |
| dc.date.accessioned | 2021-06-08T00:14:21Z | - |
| dc.date.copyright | 2013-08-06 | |
| dc.date.issued | 2013 | |
| dc.date.submitted | 2013-08-01 | |
| dc.identifier.citation | [1] R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in Deep-Submicron CMOS, New York: Wiley, 2006.
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Solid-State Circuits, vol. 45, no.3, pp. 578-586, Mar. 2010. [8] P.-Y. Wang, J.-H. C. Zhan, H.-H. Chang, and H.-M. S. Chang, “A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes,” IEEE J. Solid-State Circuits, vol. 44, no.8, pp. 2182-2192, Aug. 2009. [9] E. Temporiti, C. Weltin-Wu, D. Baldi, R. Tonietto, and F. Svelto, “A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques,” IEEE J. Solid-State Circuits, vol. 44, no.3, pp. 824-834, Mar. 2009. [10] J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, “A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI,” IEEE J. Solid-State Circuits, vol. 43, no.1, pp. 42-51, Jun. 2008. [11] C.-C. Hung, I-F. Chen and S.-I. Liu, “A 1.25GHz Fast-Locked All-Digital Phase-Locked Loop with Supply Noise Suppression,” in Proc. 2010 IEEE Int. Symp. VLSI Design Automation and Test (VLSI-DAT), Apr. 2010, pp. 237-240. [12] C.-C. Hung and S.-I. Liu, “A 35.56GHz All-Digital Phase-Locked Loop with High Resolution Varactors,” in Proc. 2010 IEEE Int. Symp. VLSI Design Automation and Test (VLSI-DAT), Apr. 2010, pp. 245-248. [13] http://www.3gpp.org/Specifications [14] D. L. Kaczman, M. Shah, N. Godambe, M. Alam, H. Guimaraes, L. M. Han, M. Rachedine, D. L. Cashen, W. E. Getka, C. Dozier, W. P. Shepherd, and Karl Couglar,“A Single-Chip Tri-Band (2100, 1900, 850/800 MHz) WCDMA/HSDPA Cellular Transceiver,” IEEE J. Solid-State Circuits, vol. 41, no.5, pp. 1122-1132, May. 2006. [15] K. Takinami, R. Strandberg, P. C. P. Liang, G. le Grand de Mercey, T. Wong, and M. Hassibi, “A Distributed Oscillator Based All-Digital PLL With a 32-Phase Embedded Phase-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 46, no.11, pp. 2650-2660, Nov. 2011. [16] X. Yu, Y. Sun, W. Rhee, H. K. Ahn, B.-H. Park, and Z. Wang, “A ΔΣ Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications,” IEEE J. Solid-State Circuits, vol. 44, no.8, pp. 2193-2201, Aug. 2009. [17] D. Tasca, M. Zanuso, G. Marzin, S. Levantino, C. Samori, and A. L. Lacaita, “A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power,” IEEE J. Solid-State Circuits, vol. 46, no.12, pp. 2745-2758, Dec. 2011. [18] H.-J. Hsu and S.-Y. Huang, “A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no.1, pp. 165-170, Jan. 2011 [19] L. Xu, K. Stadius, and J. Ryynänen, “An All-Digital PLL Frequency Synthesizer With an Improved Phase Digitization Approach and an Optimized Frequency Calibration Technique,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 11, pp. 2481–2494, Nov. 2012. [20] W. Kim, J. Park, J. Kim, T. Kim, H. Park, and D. Jeong, “A 0.032mm2 3.1mW Synthesized Pixel Clock Generator with 30psrms Integrated Jitter and 10-to-630MHz DCO Tuning Range,” in Proc. IEEE Solid-State Circuit Conf., Feb. 2013, pp. 250–252. [21] M. Zanuso, S. Levantino, C. Samori, and A. L. Lacaita, “A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation,” IEEE J. Solid-State Circuits, vol. 46, no.3, pp. 627-638, Mar. 2011. [22] M. Lee, M. E. Heidari, and A. A. Abidi, “A Low-Noise Wideband Digital Phase-Locked Loop Based on a Coarse–Fine Time-to-Digital Converter With Subpicosecond Resolution,” IEEE J. Solid-State Circuits, vol. 44, no.10, pp. 2808-2816, Oct. 2009. [23] C.-C. Chung, and C.-Y. Ko, “A Fast Phase Tracking ADPLL for Video Pixel Clock Generation in 65 nm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 46, no.10, pp. 2300-2311, Oct. 2011. [24] J.-Y. Lee, M.-J. Park, B.-H. Min, S. Kim, M.-Y. Park, and H.-K. Yu, “A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 8, pp. 1706–1719, Aug. 2012. [25] C.-C. Hung, and S.-I. Liu, “A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 58, no. 6, pp. 321–325, June. 2011. [26] http://www.etsi.org/deliver/etsi_ts/136100_136199/136101/11.04.00_60/ ts_136101v110400p.pdf [27] W. Wu, X. Bai, R. B. Staszewski, J. R. Long, “A 56.4-to-63.4GHz Spurious-Free All-Digital Fractional-N PLL in 65nm CMOS,” in Proc. IEEE Solid-State Circuit Conf., Feb. 2013, pp. 352–353. [28] G. Marzin, S. Levantino, C. Samori, and A. L. Lacaita, “A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With −36 dB EVM at 5 mW Power,” IEEE J. Solid-State Circuits, vol. 47, no.12, pp. 2974-2988, Dec. 2012. [29] L. Xu, S. Lindfors, K. Stadius, and J. Ryynänen, “A 2.4-GHz Low-Power All-Digital Phase-Locked Loop,” IEEE J. Solid-State Circuits, vol. 45, no.8, pp. 1513-1521, Aug. 2010. [30] T. Tokairin, M. Okada, M. Kitsunezuka, T. Maeda, and M. Fukaishi, “A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 45, no.12, pp. 2582-2590, Dec. 2010. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17459 | - |
| dc.description.abstract | 近年來行動裝置用戶的激增及用戶對於資訊傳輸量與使用行動性的要求提高，4G第四代Long Term Evolution (LTE)行動通訊系統能提供高資料傳輸速率及遠距離傳輸，可預見4G通訊系統即將到來。而頻率合成器提供通訊系統中收發機穩定的本地訊號源，其性能影響收機機適用的頻率範圍與雜訊表現等性能。本論文研究並設計適用於4G通訊系統之全數位頻率合成器，為整體系統提供穩定的本地訊號源。
此全數位頻率合成器可提供調變器與降頻器穩定頻率且相位鎖定訊號源，經由數位控制與使用中位數濾波器能有效地縮短頻率合成器鎖定時間、降低功率消耗與雜訊並有效達到快速且準確的跳頻。中位數數位濾波器作為電路中核心架構，藉由濾除錯誤相位資訊，大幅減少頻率合成器所需的鎖定週期數，與其他文獻相比，效能改善一倍以上。此外因頻率合成器使用數位校正補償提高對製程溫度電壓變異容忍度，以達到良好的操作特性。本論文完成了此頻率合成器整體系統模擬，並能符合LTE所要求的規格。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2021-06-08T00:14:21Z (GMT). No. of bitstreams: 1 ntu-102-R98943161-1.pdf: 4256578 bytes, checksum: eb8d1acb8b8526f4c81c58ae5cbf592d (MD5) Previous issue date: 2013 | en |
| dc.description.tableofcontents | 第一章 緒論 1
1.1 研究動機 1 1.2 頻率合成器簡介 2 1.3 LTE技術概述 5 1.4 文獻回顧 6 1.5 論文架構與貢獻 14 第二章 全數位頻率合成器架構 15 2.1 全數位鎖相迴路簡介 15 2.2 特性指標 16 2.2.1 頻率範圍 16 2.2.2 鎖定時間 17 2.2.3 相位雜訊 18 2.3 電路架構 19 2.3.1 相位頻率偵測器 19 2.3.2 數位濾波器 20 2.3.3 正規化器 21 2.3.4 數位控制震盪器 22 2.4 系統分析 23 第三章 快速鎖相迴路技術 25 3.1 鎖定技術分析 25 3.1.1 循序式鎖定技術分析 26 3.1.2 並列式鎖定技術分析 27 3.1.3 非理想效應 28 3.2 快速鎖定技術 29 3.2.1 平均數演算法 29 3.2.2 移除偏差值演算法 29 3.2.3 濾波系數設定 31 第四章 九零奈米快速鎖定頻率合成器設計 32 4.1 頻率合成器系統架構設計 32 4.1.1 應用及規格制定 32 4.1.2 系統架構 34 4.2 全數位鎖相迴路電路方塊 35 4.2.1 相位頻率偵測器 35 4.2.2 數位濾波器 44 4.2.3 平均數式正規化器 45 4.2.4 中位數式濾波器 46 4.2.5 數位控制震盪器 49 4.3 鎖定控制器設計 51 4.3.1 設計考量 51 4.3.2 快速鎖定流程圖 52 4.3.3 控制器設計 53 4.4 數位合成技術 54 4.4.1 Design Vision 55 4.4.2 IC Compiler 56 4.4.3 數位合成結果 58 第五章 模擬結果 59 5.1 Verilog模擬結果 59 5.2 Analog Mixed Signal模擬結果 63 5.3 Post Layout 模擬結果 65 第六章 結論 73 附錄 74 參考文獻 78 | |
| dc.language.iso | zh-TW | |
| dc.title | 應用於LTE通訊系統之全數位頻率合成器 | zh_TW |
| dc.title | All-Digital Frequency Synthesizer for LTE Communication System | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 101-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 郭建宏,陳昭宏,盧奕璋 | |
| dc.subject.keyword | 全數位,鎖相迴路,快速鎖定,中位數濾波器,頻率合成器, | zh_TW |
| dc.subject.keyword | All-Digital,PLL,fast-locking,median filter,frequency synthesizer, | en |
| dc.relation.page | 81 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2013-08-01 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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