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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 呂學士 | |
| dc.contributor.author | You-Nung Hsu | en |
| dc.contributor.author | 徐侑農 | zh_TW |
| dc.date.accessioned | 2021-06-08T00:01:13Z | - |
| dc.date.copyright | 2013-08-25 | |
| dc.date.issued | 2013 | |
| dc.date.submitted | 2013-08-15 | |
| dc.identifier.citation | [1] Sang-Hyun Cho; Chang-Kyo Lee; Jong-Kee Kwon; Seung-Tak Ryu; , 'A 550- 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction,' Solid-State Circuits, IEEE Journal of , vol.46, no.8, pp.1881-1892, Aug. 2011
[2] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 0.92mW10-bit 50-MS/s SAR ADC in 0.13 μm CMOS process,” in Symp. VLSI Circuits Dig. Tech. Papers, 2009, pp. 236–237. [3] B. P. Ginsburg and A. P. Chandrakasan, “An energy-efficient charge recycling approach for a SAR converter with capacitive DAC,” in Proc. IEEE ISCAS, 2005, pp. 184–187. [4] Hui Zhang; Yajie Qin; Siyu Yang; Zhiliang Hong; , 'Design of an ultra-low power SAR ADC for biomedical applications,' Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on , vol., no., pp.460-462, 1-4 Nov. 2010 [5] David A. Johns, Ken Martin, “Analog Integrated Circuit Design,” John Wiley & Sons, Inc. 1997. [6] B. Razvi, “Principles of Data Conversion System Design” IEEE Press 1995. [7] 張哲維, “Design and Application of Analog-to-Digital Converter,” National Taiwan University MS Thesis, July 2007. [8] 方柏翔, “Design and Application of Low Power Pipelined and SAR Analog-to-Digital Converters,” National Taiwan University MS Thesis, June 2009. [9] 張瀚文, “A Low Power Analog-to Digital Converter for ECG Signal Monitoring System Application,” National Taiwan University MS Thesis, July 2012. [10] Chun-Cheng Liu; Soon-Jyh Chang; Guan-Ying Huang; Ying-Zu Lin; “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure” , in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL 2010, pp. 731-740 [11] S. Jiang, M. A. Do, K. S. Yeo, and W. M. Lim, “An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 6, pp. 1430–1440, Jul. 2008. [12] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 0.92mW10-bit 50-MS/s SAR ADC in 0.13 μm CMOS process,” in IEEE Symp. VLSI Circuits Dig., Jun. 2009, pp. 236–237. [13] F. Kuttner, “A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-μm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2002, pp. 176–177. [14] B. P. Ginsburg and A. P. Chandrakasan, “Highly interleaved 5 b 250MS/s ADC with redundant channels in 65 nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 240–241. [15] Chen, S.-W.M.; Brodersen, R.W.; , 'A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13- CMOS,' Solid-State Circuits, IEEE Journal of , vol.41, no.12, pp.2669-2680, Dec. 2006. [16] H. Hong and G. Lee, “A 65-fJ/conversion-step 0.9-V 200kS/s rail-to-rail 8-bit successive approximation ADC, ”IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2161-2168, Oct. 2007. [17] Hariprasath, V.; Guerber, J.; Lee, S.-H.; Moon, U.-K.; , 'Merged capacitor switching based SAR ADC with highest switching energy-efficiency,' Electronics Letters , vol.46, no.9, pp.620-621, April 29 2010 [18] Chun-Cheng Liu; Soon-Jyh Chang; Guan-Ying Huang; Ying-Zu Lin; Chung-Ming Huang; Chih-Hao Huang; Linkai Bu; Chih-Chung Tsai; , 'A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation,' Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International , vol., no., pp.386-387, 7-11 Feb. 2010 [19] Tsung-Che Lu; Lan-Da Van; Chi-Sheng Lin; Chun-Ming Huang; , 'A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/conversion-step SAR ADC for biomedical applications,' Custom Integrated Circuits Conference (CICC), 2011 IEEE , vol., no., pp.1-4, 19-21 Sept. 2011 [20] H.–W. Chen, Y.-H. Lin, and H.-S. Chen “A 3mW 12b sub-range SAR ADC,” IEEE Asian Solid-State Circuits Conference (ASSCC), pp. 153-156, Nov. 2009 [21] Hsiang Fang; Yi Chin Li; Chang Lun Wang; Yao-Chuan Tsai; Yeong-Ray Wen; Win-Pin Shih; Yao-Joe Yang; Shey-Shi Lu Lu, “Pain Control on Demand Based on Pulsed Radio-Frequency Stimulation of the Dorsal Root Ganglion Using a Batteryless Implantable CMOS SoC,” IEEE, International Solid-State Circuit Conference (ISSCC) , San Francisco, pp. 234-235,Feb. 2010. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17211 | - |
| dc.description.abstract | 從以前到現今的社會，人類一直為了許多的疾病苦惱，無論現在還是未來，不變的是我們對生命的態度。因此，生醫方面的知識，需求將會越來越大。在這個趨勢之下，我們設計一個適合應用在生醫系統的類比數位轉換器。
在本論文的第三章，我們介紹一種採用傳統架構的單端輸入連續漸進式類比數位轉換器。 在本論文的第四章，我們介紹一套整合型的系統晶片— 刺激晶片，裡面是由各種電路所組合而成，其中也包含了類比數位轉換器。 第三章的晶片是使用 TSMC 0.18um 1P6M CMOS的製程實現。 第四章的晶片是使用 TSMC 0.35um 2P4M CMOS 的製程實現。 | zh_TW |
| dc.description.abstract | At our society from the previous to the present, we are always having trouble for many diseases. Whether now or future, it is unchangeable to our life attitude. Therefore, the demand of biomedical knowledge will get more and more. We design ADCs that are suitable for biomedical application under this trend.
In Chapter 3 of this thesis, a low power single-ended SAR ADC is presented which uses conventional structure. In Chapter 4 of this thesis, a set of integrated system-on-chip, Stimulator, is presented which contains various circuits. One of them is ADC. The chip of chapter 3 is fabricated by TSMC 0.18u, 1P6M CMOS technology and the measurement results will be shown. The chip of chapter 4 is fabricated by TSMC 0.35u, 2P4M CMOS technology and the measurement results will be shown. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T00:01:13Z (GMT). No. of bitstreams: 1 ntu-102-R00943076-1.pdf: 3845353 bytes, checksum: 30823394cb8818d3701700fd4bd18ce2 (MD5) Previous issue date: 2013 | en |
| dc.description.tableofcontents | Chapter 1 Introduction 1
1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 The fundamentals of Analog-to-Digital Converters 3 2.1 Introduction 3 2.2 ADC Performance Metrics [5][6][7][8][9] 4 2.2.1 Static Specifications 5 2.2.2 Dynamic Specifications 8 2.3 Analog-to-Digital Converter Architectures 12 2.3.1 Flash Architecture 12 2.3.2 Two-Step Architecture 13 2.3.3 Successive Approximation Architecture 14 2.3.4 Pipelined Architecture 16 2.3.5 Delta-Sigma Architecture 16 2.4 Comparison of the ADCs 17 Chapter 3 A 1-V Low Power 10-Bit SAR Analog-to-Digital Converter 19 3.1 Introduction 19 3.2 Basic Operation Principle of SAR ADC 19 3.3 Circuit Implementation of This Design 24 3.4 Circuit Building Blocks 25 3.5 SAR ADC Simulation Results 37 3.6 Measurement Result 40 3.6.1 The PCB Design 42 3.6.2 Measurement setup 43 3.6.3 The measurement of SAR ADC 43 3.6.4 Measurement results of summary 45 Chapter 4 An Implantable CMOS Multi-Purposes Nerve Stimulator 47 4.1 Introduction 47 4.2 Indication 47 4.3 Parameter of Stimulation 49 4.4 Architecture of stimulator 50 4.4.1 The Internal Block Introduction 51 4.4.2 The External Application 64 4.5 Measurement Result 65 4.5.1 The PCB Design 66 4.5.2 The Measurement of Stimulator 67 4.5.3 Measurement results of summary 75 Chapter 5 Conclusion 77 | |
| dc.language.iso | en | |
| dc.title | 應用於生醫系統之低功耗類比數位轉換器暨多功能神經刺激器 | zh_TW |
| dc.title | A Low Power Analog-to-Digital Converter for Biomedical System Application and Multi-Purposes Nerve Stimulator | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 101-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 孫台平,林佑昇,黃榮堂,孟慶宗 | |
| dc.subject.keyword | 連續漸進式,類比數位轉換器,低功耗,低電壓,刺激晶片, | zh_TW |
| dc.subject.keyword | Successive approximation,ADC,low power,low supply voltage,stimulator, | en |
| dc.relation.page | 80 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2013-08-15 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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