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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/16403完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 曹恆偉(Hen-Wai Tsao) | |
| dc.contributor.author | You-Gang Chen | en |
| dc.contributor.author | 陳右罡 | zh_TW |
| dc.date.accessioned | 2021-06-07T18:13:18Z | - |
| dc.date.copyright | 2012-06-29 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-06-21 | |
| dc.identifier.citation | [1] Y. Moon, J. Choi, K. Lee, D.-K. Jeong and M.-K. Kim , “An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 377-384, Mar. 2000.
[2] B.-G. Kim, L.-S. Kim, K.-I. Park, Y.-H. Jun and S.-I. Cho, “A DLL with jitter reduction techniques and quadrature phase generation for DRAM interfaces,” IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1522-1530, May. 2009. [3] J.-S. Wang, C.-Y. Cheng, J.-C. Liu, Y.-C. Liu, and Y.-M. Wang, “A duty-cycle-distortion-tolerant half-delay-line low-power fast-lock-in all-digital delay-locked loop,” IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 1036-1047, May. 2010. [4] H.-H. Chang and S.-I. Liu, “A wide-range and fast-locking all-digital cycle-controlled delay-locked loop,” IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 661-670, Mar. 2005. [5] S.-K. Kao and S.-I. Liu, “A 62.5-625-MHz anti-reset all digital delay-locked loop,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 7, pp. 566-570, Jul. 2007. [6] A. Hatakeyama, H. Mochizuki, T.Aikawa, and M. Takita, “A register-controlled symmetrical DLL for double-data-rate DRAM,” IEEE J. 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Kim, “A 100 MHz-to-1 GHz Fast-Lock Synchronous Clock Generator with DCC for Mobile Applications,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.58, no.8, pp.477-481, Aug. 2011. [45] M. Y. Kim, D. Shin, H. Chae, and C. Kim, “A low-jitter open-loop all-digital clock generator with two-cycle lock-time,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 10, pp. 1461–1469, Oct. 2009. [46] Jinn-Shyan Wang, et al., “A 55nm 1GHz one-cycle-locking de-skewing circuit,” in Proc. IEEE Int. Symp. Circuits and Systems, pp. 1755-1758, May 2010. [47] D. Shin, W. J. Yun, H. W. Lee, Y. J. Choi, S. Kim, and C. Kim, “A 0.17–1.4 GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme,” in Proc. Euro. Solid-State Circuits Conf., Sept. 2008, pp. 82–85. [48] K.-J. Hsiao and T.-C. Lee, “An 8-GHz to 10-GHz distributed DLL for multiphase clock generation,” IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2478–2487, Sep. 2009. [49] W.-H. Chiu, Y-H. Huang, and T.-H. Lin, “A dynamic phase error compensation technique for fast-locking phase-locked loops,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1137–1149, Jun. 2010. [50] P. Bhoraskar and Y. Chiu, “A 6.1-mW dual-loop digital DLL with 4.6-ps RMS jitter using window-based phase detector,” in IEEE Asian Solid-State Circuits Conf., Nov. 2007, pp. 79–82. [51] Hyun-Woo Lee and Yong-Hoon Kim , “A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface,” in Proc. IEEE Int. Symp.Circuits and Systems, May 30 2010, pp.3861-3864. [52] Yi-Ming Wang, Jen-Tsung Yu,and Chung-Hsun Huang, “A Compact Delay-Recycled Clock Skew-Compensation And/Or Duty-Cycle-Correction Circuit,” in Proc. IEEE International SOC Conf., Sep 2011, pp. 42-47. [53] Keun-Soo Song and Byong-Tae Chung, “A single-loop DLL using an OR-AND duty-cycle correction technique,” in IEEE Asian Solid-State Circuits Conf., Nov. 2008, pp. 245–248. [54] Dong-Uk Lee and Joong-Sik Kih, “A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb 2006, pp. 547-556. [55] Hyun-Woo Lee and Byong-Tae Chung, “A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb 2011, pp. 502-504 [56] Jang-Jin Nam and Hong-June Park, “An all-digital CMOS duty cycle correction circuit with a duty-cycle correction range of 15-to-85% for multi-phase applications,” IEICE Trans. on Electronics, vol. E88-C,no.4, pp. 773-777. Apr. 2005. [57] S.-K. Kao and S.-I. Liu, “All-digital clock deskew buffer with variable duty cycles,” IEICE Trans. on Electronics, vol. E89-C, no.6, pp. 753-759. Jun. 2006. [58] Jun-Hyun Bae and Hong-June Park, “An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface,” in Proc. IEEE Custom Integr. Circuits Conf. Dig. Tech. Papers, pp. 373-376, Sep. 2007. [59] T-H Lin and C-C Chi, “A Synchronous 50% Duty-Cycle Clock Generator in 0.35-um CMOS,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.19, no.4, pp.585-591, April 2011. [60] S. Duo and C.-Y. Lee, “Wide duty cycle range synchronous mirror delay designs,” Electronics Letters , vol.46, no.5, pp.338-340, Mar. 2010. [61] C.-C. Chung and C.-Y. Lee, “A wide-range all-digital delay-locked loop in 65nm CMOS technology,” in IEEE Int. Symp. VLSI Design, Automation & Test, Apr. 2010, pp.66-69. [62] C.-C. Chung and C.-Y. Lee, “An All-Digital Delay-Locked Loop for DDR SDRAM Controller Applications,” in IEEE Int. Symp. VLSI Design, Automation & Test, Apr. 2006, pp. 26-28. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/16403 | - |
| dc.description.abstract | 隨著CMOS製程技術的發展和進步，高度整合的系統晶片在操作速度及效能上不斷地提昇，時脈誤差所造成時脈不同步現象也因操作速度的增加，而嚴重威脅系統運作的正確性，因此，IC內部與模組間的時脈同步課題，也相形更加的重要。在雙倍取樣的系統中，例如靜態記憶體和類比到數位轉換器，具有50%工作週期的訊號是非常重要的。因此，除了時脈訊號同步的問題外，時脈訊號之責任週期也需要被精準的控制，以提高電路操作之可靠度與正確性。
在本論文中，我們首先提出了同時實現時脈訊號同步與責任週期修正的去時脈誤差緩衝電路。藉由分析傳統使用兩組半延遲線的責任週期校正技術在製程漂移下導致延遲線不匹配所造成影響，並提出了三組延遲線與內差的方法來解決。為了達到快速鎖定，我們使用了一組循環式時間至數位轉換器在兩個參考時脈週期裡完成的責任週期的粗調。另外，我們提出了一個設定與重置訊號路徑相等的平衡式邊緣合成器來降低輸出訊號責任週期的失真。 另外，我們也實現了一大操作範圍下依然可以快速鎖定，且不會造成諧波鎖定的延遲鎖定迴路。本論文分析了除率對鎖定時間的影響，並提出了快速最大有效位元位置決定電路，使除率能維持最小值，並解決了諧波鎖定的問題。此外，可適性數位控制延遲線可根據操作頻率來調整延遲線的本質延遲，因而提高了電路的操作頻率。我們也提出可適性連續近似控制器，來搭配快速最大有效位元位置決定電路所取得的控制碼，依據不同操作速度調整二元搜尋法的長度，因而減少鎖定時間。 最後提出了與責任週期無關的快速鎖定之時脈訊號同步電路。我們使用了二級時脈誤差的補償方式：在第一級中，提出了一個具有省電設計的粗偏移補償電路，可利用單延遲線實現並且具備快速鎖定性能。為了減少鎖定時間與提高解析度，我們提出了非同步線性搜尋電路和差分延遲線的細偏移補償電路。 為了驗證以上所提出的三個全數位延遲鎖定迴路電路理論與架構，我們使用0.18微米的互補式金氧半導體製程來進行晶片設計與實現，測試結果均驗證其可行性並同時具有快速鎖定功能。 | zh_TW |
| dc.description.abstract | With the evolution and the advancement of the complementary metal-oxide (CMOS) semiconductor process technologies, the performance and the operating frequency of the highly integrated system-on-a-chip (SoC) are raised higher and higher. The clock skew will cause the incorrect system operation seriously due to the asynchronous clocks. Thus, the aligning problem among IC modules and IPs in the SoC or system designs is becoming one of the bottlenecks for high performance systems. In double-sampling systems, like the DDR memory, the clock with the exact 50% duty cycle is very important. Consequently, the duty-cycle correction (DCC) plays an important role in such systems. In addition to the clock skew problem, the clock duty cycle also needs to be controlled accurately to improve the reliability and correctness of circuits
At first, a deskew buffer with DCC is proposed and realized. With the analysis of the impact on the duty cycle due to the delay line mismatch in conventional two half-delay line architecture, a new concept using three half-delay lines to alleviate the duty-cycle distortion is introduced to overcome the process variation. With the aid of a cyclic time-to-digital converter, the coarse locking time is reduced to only two cycles. A balanced-path edge combiner to produce a precise 50% output clock is also presented. To obtain the wide-range, fast-locking, and harmonic-free functions, an all-digital delay-locked loop is proposed. A fast MSB decision circuit is designed to minimize the division ratio and to prevent harmonic-locking. Then, by using an adaptive digital-controlled delay line which can tune the intrinsic delay dynamically, the speed of DLL operation can be expanded. Furthermore, the adaptive SAR controller can change the binary search length with the operating frequency such that the locking time is reduced. Finally, a duty-cycle independent fast-locking all-digital deskew buffer with an asynchronous linear search technique is presented. A coarse skew compensation circuit with a power-efficient design is proposed to achieve fast-locking. To reduce the fine compensation time with a higher resolution, the fine skew compensation circuit to realize the asynchronous linear search algorithm with the delay difference technique is designed to achieve fast-locking capability. To verify the proposed circuit theories and architectures of the three all-digital DLLs described above, the test chips have been designed and fabricated using the CMOS 0.18μm process technology. The measured results of the chips prove the feasibility with the fast-locking capability | en |
| dc.description.provenance | Made available in DSpace on 2021-06-07T18:13:18Z (GMT). No. of bitstreams: 1 ntu-101-D93943020-1.pdf: 4188442 bytes, checksum: f1c6fd0b1d3743623596cb2914ad8e2b (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | Chapter 1. Introduction 1
1.1. Background 1 1.2. Motivation 2 1.3. Dissertation Organization 3 Chapter 2. The Fundamentals of Delay-Locked Loops 5 2.1. Clock Skew 5 2.2. Overview of Analog Delay-Locked Loop 8 2.2.1. Analysis of Analog Delay-Locked Loop 9 2.3. Design Consideration of Delay-Locked Loop 11 2.3.1. Harmonic-Locking and Stuck-Locking Problems 12 2.3.2. Locking Time 14 2.3.3. Jitter Performance 16 2.4. Review on Digital Delay-Lock Loop 20 2.4.1. Register-Controlled DLL 20 2.4.2. Counter-Controlled DLL 22 2.4.3. Successive Approximation Register-Controlled (SAR ) DLL 23 2.4.3.1. Time-to-Digital Based (TDC) DLL 24 Chapter 3. A Fast-Locking All-Digital Deskew Buffer with Duty-Cycle Correction 27 3.1. Analysis of Delay Lines in Deskew Buffer and DCC 27 3.1.1. Delay Lines in Deskew Buffer 27 3.2. System Architecture and Principle of Operation 35 3.2.1. Proposed Architecture 35 3.2.2. Edge Interpolation using Three Half-Delay Lines 36 3.2.3. Operating Sequences 39 3.3. Circuit Implementation 40 3.3.1. Half-delay Line (HDL) 41 3.3.2. Cyclic Time-to-Digital Converter (CTDC) 44 3.3.3. Edge Combiner and Interpolator 49 3.3.4. Phase Detector 53 3.3.5. Quad-State Controller 55 3.4. Experimental Results 58 3.5. Conclusion 60 Chapter 4. A Wide-Range, Fast-Locking, and Harmonic-Free All-Digital Delay-Locked Loop with an Adaptive SAR Controller 67 4.1. Locking Time and Division Ratio of Conventional SAR DLLs 67 4.1.1. The State of the Art 71 4.2. System Architecture and Operating Principle 72 4.2.1. Proposed Architecture 72 4.2.2. Proposed Algorithm 73 4.3. Circuit Implementation 80 4.3.1. Coarse Delay Line 80 4.3.2. Fine Delay Line 83 4.3.3. Fast MSB Position Decision Circuit (FMPDC) 85 4.3.4. Adaptive SAR Controller (ASAR) 87 4.3.5. Adaptive Binary-Weighted Digital-Controlled Delay Line (ADCDL) 87 4.4. Experimental Results 90 4.5. Conclusion 92 Chapter 5. A Duty-Cycle Independent Fast-Locking All-Digital Deskew Buffer with an Asynchronous Linear Search Technique 98 5.1. Analysis of Conventional Fast-Locking Deskew Buffer 98 5.2. System Architecture and Operation Principle 105 5.2.1. Coarse Skew Compensation 107 5.2.2. Fine Skew Compensation 111 5.2.3. Timing Analysis and Operating Range. 116 5.2.4. Operating Frequency Range 120 5.3. Circuit Implementation 121 5.3.1. Difference Delay Line 121 5.3.2. Multiplexer 122 5.3.3. Arbiter 123 5.3.4. Timing Capture Circuit and Step controller 125 5.4. Experimental Results 126 5.5. Conclusion 128 Chapter 6. Conclusion and Future Work 137 6.1. Conclusion 137 6.2. Future Work 138 APPENDIX A Locking Time of Previous Works 140 Bibliography 142 | |
| dc.language.iso | en | |
| dc.title | 具快速鎖定能力之全數位延遲鎖定迴路設計與分析 | zh_TW |
| dc.title | Design and Analysis of All-Digital Delay-Locked Loops with Fast-Locking Capability | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-2 | |
| dc.description.degree | 博士 | |
| dc.contributor.coadvisor | 黃崇禧(Chorng-Sii Hwang) | |
| dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),張振豪(Chen-Hao Chang),陳伯奇(Poki Chen),陳建中(Jiann-Jong Chen),楊?頡(Ring-Jyi Yang) | |
| dc.subject.keyword | 互補式金氧半導體,系統晶片,時脈誤差,鎖相迴路,延遲鎖定迴路,雙倍取樣,責任週期校正電路,半延遲線,循環式時間至數位轉換器,諧波鎖定,可適性連續近似控制器, | zh_TW |
| dc.subject.keyword | CMOS,SoC,clock skew,PLL,DLL,double-edge trigger,duty cycle corrector,half-delay line,cyclic time-to-digital converter,wide range,harmonic lock,adaptive,successive approximation register controller (SAR), | en |
| dc.relation.page | 149 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2012-06-21 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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