CMOS MEMS 低偏壓電容式超音波感測器開發

Abstract

本研究利用電容式微機電超音波換能器(CMUTs)原理，結合TSMC CMOS 0.35製程，開發一種新式電容式微機電超音波感測器(CMUS)。感測結構於CMOS晶圓底部階層製作，以多晶矽層作為結構犧牲層，搭配上部金屬十字交叉犧牲層設計。經由濕蝕刻後製程處理，成功釋放位於晶圓底部的電容式薄膜結構。另外結合底部金屬層的佈局，使感測器等效中空層間距減少，大幅度的降低感測器操作偏壓(0~5V)。 再者本研究提出一種介於犧牲層與蝕刻洞之間的新式蝕刻裝置：蝕刻槽。經由蝕刻槽使犧牲層露出的面積增加，有效地提高感測器後製程速度與良率。另一方面，搭配微小蝕刻洞(0.5μm×0.5μm)的使用，元件防水封裝製程可以輕易的完成，讓感測器的製作更加的穩定。 最後感測元件以打線的方式整合CMOS 0.18後端放大電路，完成超音波感測整合電路。此感測收電路有效地降低電路寄生電容並提高訊雜比。為了消除充電效應的影響，施加交流偏壓於感測電路進行量測。獲得訊雜比為45.54dB，頻寬比為112.88%以及中心頻為7.39MHz的量測結果。

This paper presents a successful achievement on lowering bias voltage of CMUS (capacity micromachined ultrasound sensor). By using the TSMC CMOS 0.35 process and etching post-process the devices are fabricated on the CMOS chips bottom layers. Based on the CMUTs’ construct theory, we etch the top cross-metal layers and polysilicon layer to release the membrane. By polysilicon layer etching and adding contact as the part of top electrode, the equivalent gap will be reduced and the bias voltage will decrease obviously (0~5V). Furthermore, we propose a novel structure between etching holes and sacrificial layer. The structure called etching ditch improves the etching rate and yield by exposing larger area when wet etching. On the other hand, the device will be easily water-proven due to the small size of etching hole (0.5um*0.5um) over the ditch. Also, by wire-bonding with CMOS ASIC fabricated in TSMC 0.18-μm CMOS process, the integrated sensing circuit reduces the parasitic capacitance and enhances the signal to noise ratio effectively. For reducing the charging effect of the devises, an alternating bias voltage is applied, and the characterization of CMOS-electronics shows the large fractional bandwidth (112.88%) and 45.54dB signal to noise ratio in the 7.39MHz resonant frequency.