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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳安宇 | |
| dc.contributor.author | Ming-Han Chung | en |
| dc.contributor.author | 鍾明翰 | zh_TW |
| dc.date.accessioned | 2021-06-07T18:03:07Z | - |
| dc.date.copyright | 2012-08-07 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-07-31 | |
| dc.identifier.citation | [1] G. Wong, “NAND Flash Memory: Enabling Mobility,” Sep. 2009, [online]. Available: http://www.forward-insights.com/present/Wong-Diskcon_0909.pdf
[2] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells-an overview,” Proc. IEEE, vol. 85, no. 8, pp. 1248-1271, Aug. 1997. [3] N. Mielke et al, “Bit error rate in NAND flash memories,” in Proc. IEEE Int. Rel. Phys. Symp. (IRPS), pp. 9-19, April 2008. [4] Solid-State Drive (SSD) Requirements and Endurance Test Method, JEDEC Standard JESD218A, Sep. 2010. [5] R. Micheloni, A. Marelli, and R. Ravasio, Error Correction Codes for Non-Volatile Memories. Springer, 2008. [6] Y. Maeda and H. Kaneko, “Error control coding for multilevel cell flash memories using nonbinary low-density parity-check codes,” in IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, pp. 367-375, Oct. 2009. [7] S.-L. Chen, B.-R. Ke, J.-N. Chen, and C.-T. Huang, 'Reliability analysis and improvement for multi-level non-volatile memories with soft information,' in ACM/EDAC/IEEE Design Automation Conf. (DAC), pp.753-758, June 2011. [8] J. Wang, T. Courtade, H. Shankar, and R. Wesel, “Soft information for LDPC decoding in flash: mutual-information-optimized quantization,” in Proc. IEEE Global Commun. Conf. (GLOBECOM), pp. 1-6, Dec. 2011. [9] R. Gallager, “Low-Density Parity-Check Codes,” IRE Trans. Inf. Theory, vol. 7, pp. 21–28, Jan. 1962. [10] D. J. C. MacKay and R. M. Neal, 'Good codes based on very sparse matrices', Cryptography and Coding 5th IMA Conf., no. 1025, pp.100 - 111, 1995. [11] T. J. Richardson, A. Shokrollahi, and R. Urbanke, 'Design of capacity-approaching low-density parity-check codes', IEEE Trans. Inform. Theory, vol. 47, no. 8, pp. 619-637, Feb. 2001. [12] M. Fossorier, 'Quasi-cyclic low-density parity-check codes from circulant permutation matrices,' IEEE Trans. Inform. Theory, vol. 50, no. 8, pp. 1788-1793, Aug. 2004. [13] O.N.F.I. Workgroup, 'Open NAND flash interface (ONFi) specification,' Technical Report Revision 2.2, 2010. [14] R. M. Tanner, “A recursive approach to low complexity codes,” IEEE Trans. Inform. Theory, vol. IT-27, pp. 533–547, Sept. 1981. [15] W. E. Ryan and S. Lin, Channel Codes: Classical and Modern. Cambridge University Press, 2009. [16] Z. Li, L. Chen, L. Zeng, S. Lin, and W. Fong, “Efficient encoding of quasi-cyclic low-density parity check codes,” IEEE Trans. Commun., vol. 54, no. 1, pp. 71–81, Jan. 2006. [17] M. P. C. Fossorier, M. Mihaljevic, and H. Imai, “Reduced complexity iterative decoding of low density parity check codes based on belief propagation,” IEEE Trans. Commun., vol. 47, no. 5, pp. 673-680, May 1999. [18] J. Chen, A. Dholakia, E. Eleftheriou, M. P. C. Fossorier and X.-Y. Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Commun., vol. 53, no. 8, pp. 1288-1299, Aug. 2005. [19] M. M. Mansour “A turbo-decoding message-passing algorithm for sparse parity-check matrix codes,” IEEE Trans. Signal Process., vol. 54, no. 11, pp.4376-4392, Nov. 2006. [20] D.E. Hocevar, 'A reduced complexity decoder architecture via layered decoding of LDPC codes,' in IEEE Workshop on Signal Processing Systems (SIPS), pp. 107- 112, Oct. 2004. [21] K. Gunnam, G. Choi, M. Yeary, and M. Atiquzzaman, “VLSI architectures for layered decoding for irregular LDPC codes of WiMax,” in Proc. IEEE Int. Conf. Commun. (ICC), pp. 4542–4547, June 2007. [22] Y. Sun, M. Karkooti, and J. Cavallaro, 'High throughput, parallel, scalable LDPC encoder/decoder architecture for OFDM systems,' in IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software, pp. 39-42, Oct. 2006. [23] S. Kim, G.E. Sobelman, and H. Lee, “A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes,” IEEE Trans. VLSI Syst., vol. 19, no. 6, pp.1099-1103, June 2011. [24] B. Xiang, D. Bao, S.-Q Huang, and X.-Y Zeng, “An 847-955Mb/s 342-397mW dual-path fully-overlapped QC-LDPC decoder for WiMAX system in 0.13um CMOS,” IEEE J. Solid-State Circuits, vol.46, no. 6, pp. 1416–1432, June. 2011. [25] C. Studer, N. Preyss, C. Roth, and A. Burg, “Configurable high-throughput decoder architecture for quasi-cyclic LDPC codes,” in Proc.42nd Asilomar Conf. on Signals, Systems and Computers, Oct. 2008, pp.1137–1142. [26] L. H. Miles, J. W. Gambles, G. K. Maki, W. E. Ryan, and S. R. Whitaker, “An 860-mb/s (8158,7136) low-density parity-check encoder,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1686–1691, Aug. 2006. [27] C.-H. Lin, C.-Y. Chen, and A.-Y. Wu, “Area-efficient scalable MAP processor design for high-throughput multistandard convolutional turbo decoding,” IEEE Trans. VLSI Syst., vol. 19, no. 2, pp. 305-318, Feb. 2011. [28] M. M. Mansour and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE J. Solid-State Circuits, vol.41, no. 3, pp. 634–698, Mar. 2006. [29] X.-Y. Shih, C.-Z. Zhan, and A.-Y. Wu, “A Real-Time Programmable LDPC Decoder Chip for Arbitrary QC-Based Parity Check Matrices,” in Proc. IEEE Asian Solid-State Circuits Conf. (ASSCC), pp. 369-372, Nov. 2009. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/16155 | - |
| dc.description.abstract | 近年來包含多階儲存(MLC)快閃記憶體的非揮發性記憶體系統，因為具有高儲存密度、高效能與低功率消耗的優點，特別適用於消費型電子產品的應用。然而，多階儲存快閃記憶體的高錯誤率特性也嚴重影響了非揮發性記憶體系統的可靠度。對於此問題，低密度奇偶校驗碼(LDPC codes)因具有優越的錯誤更正能力，被認為是未來高容量非揮發性記憶體系統中錯誤更正碼(ECC)的優良候選人。
但在實際應用上，有如下問題仍待解決：(1) 低密度奇偶校驗碼解碼時須搭配軟性值(soft values)才能得到最佳的錯誤更正能力。然而現今快閃記憶體的輸出入介面僅提供硬性值(hard values)。使用硬性值對低密度奇偶校驗碼解碼會造成其錯誤更正能力大幅下降。(2) 低密度奇偶校驗碼的編解碼器需要大量的記憶體單元，而該記憶體的大小又與碼字(codeword)的長度成正比。因此非揮發性記憶體系統的長碼字特性將大幅增加低密度奇偶校驗碼編解碼器的記憶體成本。(3) 現今在非揮發性記憶體系統中對於低密度奇偶校驗碼仍無統一之規格與標準，為了降低硬體重新設計的成本與提供快速驗證的原型設計，可重組化的編解碼器設計也是被期望的。 本論文的主要貢獻包含下列兩個部分：(1) 我們提出基於狀態轉變的軟性值估計方法。使用估計的軟性值進行低密度奇偶校驗碼的解碼，不僅提供較硬性值解碼更佳的錯誤更正能力，也可趨近於使用完美軟硬值解碼的效能。(2) 我們針對非揮發性記憶體系統的錯誤更正碼應用，提出一具有成本效率與吞吐量(throughput)增強之可重組化半循環低密度奇偶校驗(QC-LDPC)編解碼器架構設計。相較於傳統架構，我們所提出的編解碼器架構大幅減少了記憶體成本並可增強吞吐量。而在預先定義好的參數空間中，可重組化的架構設計可支援任意的半循環低密度奇偶校驗碼。 最後，我們利用台積電 90奈米製程實作一個可重組化半循環低密度奇偶校驗編解碼器的原型設計。編碼器與解碼器晶片面積分別為0.32mm2與2.58mm2。在138.8MHz的操作頻率下與設定為最長的碼字長度時，編碼器可達到1110Mb/s的資料吞吐量，而解碼器在8次疊代時，可達到393Mb/s的資料吞吐量。 | zh_TW |
| dc.description.abstract | Recently, non-volatile memory systems (NVMS) with multi-level cell (MLC) NAND flash memories have greatly prevailed among consumer electronics products for their high storage density, high performance, and low power consumption. However, the high error-rate characteristic of MLC NAND flash memories also degrades the reliability of NVMS significantly. To overcome this problem, low-density parity-check (LDPC) codes are regarded as good candidates for the error correcting code (ECC) in future high-capacity NVMS due to their superior error-correcting performance.
In practice, there are some problems to be solved before adopting LDPC codes in NVMS. (1) The superior error-correcting capability of LDPC codes comes from decoding with soft values. However, the I/O interface of flash memories currently only provides hard values. The error correcting performance of decoding LDPC codes with hard values is much worse. (2) An LDPC codec is a memory-dominant design, and the memory size of codec is linearly proportional to the codeword size. The large codeword size in NVMS may greatly increase the memory cost of a LDPC codec. (3) There is still no standardized LDPC code for NVMS. To reduce the hardware redesign cost and provide a rapid prototyping for evaluation, a codec design with reconfigurability is desirable. The contributions of this thesis consist following two parts: (1) We propose state-transition-based soft value estimation schemes to generate estimated soft values for decoding LDPC codes. With the estimated soft value, the error correcting performance not only is better than that with hard values, but also approaches that with perfect soft values. (2) Targeted for ECCs in NVMS, cost-effective we propose throughput-enhanced reconfigurable architecture designs for quasi-cyclic LDPC (QC-LDPC) codec. The proposed codec architectures significantly reduce the area cost of memories and has higher throughput compared to conventional QC-LDPC codec designs. Moreover, the proposed reconfigurable architectures support arbitrary QC-LDPC codes within a pre-defined parameter space. A prototyping reconfigurable QC-LDPC codec is designed and implemented in TSMC 90nm process. The core area of encoder and decoder are 0.32mm2 and 2.58 mm2, respectively. Operating at a clock frequency of 138.8MHz and configured to the maximum codeword size, the encoder attains a throughput of 1110Mb/s, and the decoder attains a throughput of 393Mb/s at 8 iterations. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-07T18:03:07Z (GMT). No. of bitstreams: 1 ntu-101-R99943018-1.pdf: 3082038 bytes, checksum: e742699bbadd5a48ffb6657d28a942ff (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | 口試委員會審定書 ....................................i
致謝..............................................iii 摘要...............................................v Abstract..........................................vi Contents........................................viii List of Figures...................................xi List of Tables...................................xiv Chapter 1 Introduction.......................1 1.1 Non-Volatile Memory Systems................1 1.1.1 NAND Flash Memory..........................1 1.1.2 Error Correcting Codes (ECCs) for Non-Volatile Memory Systems.....................................4 1.2 Motivation and Contributions...............6 1.3 Thesis Overview.................................... 8 Chapter 2 Low-Density Parity-Check (LDPC) Codes... 10 2.1 Fundamentals of LDPC Codes..............10 2.2 Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) Codes...........................................12 2.3 Encoding of LDPC Codes.....................14 2.4 Decoding of LDPC Codes.....................16 2.4.1 Two-Phase Message-Passing (TPMP) Algorithm.....17 2.4.2 Turbo-Decoding Message-Passing (TDMP) Algorithm 19 2.4.3 Comparison.................................22 2.5 Summary...............................................26 Chapter 3 Proposed State-Transition-Based Soft Value Estimation Schemes for Non-Volatile Memory Systems...... 28 3.1 Introduction to Hard Value and Soft Value.....28 3.2 Proposed State-Transition-Based Soft Value Estimation Schemes....................................30 3.2.1 Basic State-Transition Model for Flash Memory Cells 31 3.2.2 Soft Value Estimation Derived from the Proposed Basic State-Transition Model..........................34 3.2.3 Extended State-Transition Model for Flash Memory Cells 35 3.2.4 Soft Value Estimation Derived from the Proposed Extended State-Transition Model 39 3.3 Simulation and Performance Evaluation 39 Chapter 4 Proposed Reconfigurable QC-LDPC Encoder Designs 42 4.1 Encoder Architectures with Generator Matrix in Systematic-Circulant Form..........................42 4.2 Proposed Encoder Architectures.............46 4.2.1 Proposed Reconfigurable Partial-Parallel (RPP) Parity Generator................................46 4.2.2 Proposed Shared-Memory Architecture for Circulant Memory..........................................49 4.3 Synthesis Results and Comparison....... 52 Chapter 5 Proposed Reconfigurable QC-LDPC Decoder Design........54 5.1 Decoder Architectures with the TDMP Algorithm...54 5.2 Proposed Decoder Architectures..................59 5.2.1 Proposed Re-arranged Architecture...............60 5.2.2 Proposed Reconfigurable Architecture............61 5.2.3 Proposed Column-based Early Termination Scheme..63 5.3 Synthesis Results and Comparison....... ........66 Chapter 6 Chip Implementation.....................70 6.1 Chip Results.................................................70 6.2 Comparison........................................... 71 Chapter 7 Conclusions and Future Work.............74 7.1 Conclusions........................................... 74 7.2 Future Work.......................................... 75 References.......................................77 | |
| dc.language.iso | en | |
| dc.subject | 低密度奇偶校驗碼 | zh_TW |
| dc.subject | 非揮發性記憶體系統 | zh_TW |
| dc.subject | low-density parity-check (LDPC) codes | en |
| dc.subject | non-volatile memory systems | en |
| dc.title | 適用於非揮發性記憶體系統的可重組化半循環低密度奇偶校驗編解碼器之演算法與硬體架構設計 | zh_TW |
| dc.title | Algorithms and Architectures of Reconfigurable QC-LDPC Codec for Non-Volatile Memory Systems | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 趙啟超,賴瑾,王忠炫 | |
| dc.subject.keyword | 非揮發性記憶體系統,低密度奇偶校驗碼, | zh_TW |
| dc.subject.keyword | non-volatile memory systems,low-density parity-check (LDPC) codes, | en |
| dc.relation.page | 80 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2012-07-31 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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