高遷移率鍺金氧半場效電晶體之製備與特性

Abstract

近代半導體工業跟隨著莫爾定律的規則，持續地將元件微縮(Scaling)進化。但傳統的矽金氧半場效電晶體(MOSFETs)技術已經逐漸面對其微縮的極限。為了要持續維持著元件微縮的步調，必須要開發更高載子遷移率(Carrier Mobility)的新材料來取代傳統矽做為元件通道材料，像鍺或是其他三五族的高載子遷移率材料目前受到相當的矚目，而其中鍺它擁有優越的高遷移率電子與電洞，更是被認為能在未來使用於22奈米節點製程以取代矽。然而，鍺元件仍然存在著許多難題需要克服，其中主要的是高介電係數材料(High-k)的製程整合，n型參雜物(Dopants)的活化改善，表面鈍化的處理，以及適當的應變(Strain)技術。 本論文中，我們利用了高速熱氧化法(RTO)來成長二氧化鍺(GeO2)做為鍺與高介電系數材料的介面層(Interfacial Layer)，接著使用了臭氧為基底的低溫原子沉積(ALD)來生長三氧化二鋁(Al2O3)來保護並增進二氧化鍺的品質，其效應可由鍺金氧半電容元件的電容特性量測得知，而我們也做了以氧氣為基底的低溫原子沉積來生長三氧化二鋁的金氧半電容元件比較以確認臭氧的效應。此外，我們利用了高速熱退火(RTA)來活化離子佈值並成功製作了高開關比率的n+/p二極體，其二極體的理想因子為1.06代表接面中的缺陷很少。 先前許多研究中的鍺n型金氧半元件並沒有表現出其高載子遷移率的特性。而我們利用了二氧化鍺使鍺的表面鈍化，並使用了臭氧對閘極層進行處理，以及使用高速熱退火來活化源極以及汲極的離子佈值區，成功的使高介電係數介電質與閘極最後製程整合到鍺基板上，並在鍺的(100)基板上製作出了有高遷移率電子的鍺金氧半場效電晶體元件。元件中的介面品質可由電導方法量測得知。閘極中不同厚度二氧化鍺的元件表現出相同的表面粗糙散射(Surface Roughness Scattering)效應。而對於元件加了適當的應力後，藉由產生鍺的能帶分裂(Band Splitting)以及電子重新分佈(Electron Repopulation)可再使載子遷移率提升。 n型鍺金氧半場效電晶體元件在(111)方向的基板上擁有最高的載子遷移率，我們成功的製作了超過傳統矽2倍載子遷移率的金氧半場效電晶體元件在鍺(111)基板上，而基板參雜濃度與載子遷移率的關係也由實驗上證實。

Recently, semiconductor industry technology has followed the path of scaling trend based on Moore’s law. But conventional bulk Si MOSFETs is approaching its fundamental scaling limits. For the continued of the scaling trend, high mobility materials have been comprehensively investigated as channel material for replacing Si, such as Ge or III-V material due to its high intrinsic carrier mobility. Ge has become a promising candidate to be use on 22nm nodes for beyond CMOS technology, because it has high electron and hole mobility on bulk substrate. At the same time, there are several critical issues for Ge device. The primary challenges to achieve high mobility Ge MOSFETs are the high-k integration process, the improvement of n-type dopants activation, reduction of interface traps density, and proper strain configuration. In this thesis, rapid thermal oxidation is used as the fast and effective Ge interface passivation. Al2O3 as high-k layer is deposited by atomic-layer-deposition (ALD) using ozone as oxidant at low temperature. It could improve the interface quality of Ge metal-insulator-semiconductor (MIS) capacitors. The effect of ozone treatment is confirmed by comparing with the control samples which Al2O3 was deposited by using O2 as oxidant. The electrical characterizations by dispersion-free C-V curves of Ge MISCAPs are investigated. Moreover, high on/off ratio n+/p diodes were fabricated by ion-implantation and rapid thermal annealing for activation. The ideality factor of ~1.06 and high on/off ratio of ~106 are obtained, indicating low defects within the junction. The performances of Ge n-MOSFETs do not reach its potential of high mobility in many previous studies. In this work, with GeO2 passivation, ozone treatment, rapid thermal annealing on Source/Drain activation and gate-last integration process with high-k dielectrics, Ge n-MOSFETs demonstrating high peak electron mobility (~ 976 cm2/V-s) for Ge (001) substrate and excellent electrical transistor behaviors are fabricated. Effects of interface states are demonstrated by conductance method. Ge MOSFETs which GeO2 with various thicknesses in gate stack exhibit the same interface roughness scattering behavior. Proper stress further boosts the mobility enhancement by band splitting and electron repopulation. Ge (111) n-MOSFETs that achieved highest electron mobility among all different orientation may be investigated. The peak mobility reaches 2200 cm2/V-s, ~2 times of the Si universal mobility, of Ge MOSFETs on (111) substrates is demonstrated. Substrate doping dependence of electron mobility also experimentally investigated.