雙模式CMOS數位脈波寬度調變器

Abstract

本論文提出新的數位脈波寬度調變器架構，以應用於手機功率放大器系統上。規格要求的工作頻率為30-150 MHz，且需有180°相位差的雙相位訊號輸出，脈波寬度調變型態則為雙緣調變形式。為了因應此規格，本論文第一部份提出一個六位元的延遲線型數位脈波寬度調變器電路設計，並且使用TSMC 0.18-um CMOS製程實做。架構上使用延遲鎖相迴路產生64相位訊號輸出，利用此64相位訊號的相位差經由NAND和AND邏輯閘調變出所需要的脈波寬度調變訊號。此架構可以同時產生出180°相位差的雙相位訊號輸出，省去需另外再製造另一相位訊號輸出的電路面積。 為了在工作頻率30 MHz時提昇解析度至八位元，本論文第二部份提出分段式延遲線型的數位脈波寬度調變器，使用TSMC 90-nm CMOS製程製作。架構採用分段式的延遲線架構來減少延遲元件個數，降低晶片面積大小。最後量測出的電路效能在八位元解析度，工作頻率30 MHz時，INL為15.9 ~ -20.2，DNL為22 ~ -20.3。六位元解析度，工作頻率150 MHz時，INL為1.29 ~ -0.94，DNL為1.05 ~ -0.62。

This thesis presents a new digital pulse-width modulator (DPWM) architecture applied for RF power amplifier in mobile communication system. The clock frequency of the DPWM is 30-150 MHz. It has dual-phase signal outputs with 180° phase difference. In addition, the pulse-width modulation scheme is dual-edge modulation. The first part of this thesis proposed a 6-bit delay-line based DPWM using TSMC 0.18-um CMOS process. A delay-locked loop produces a 64-phase signal output, and using the phase difference of 64 phase signals through NAND and AND logic gates generates the pulse-width modulation signal. This structure can generate dual-phase pulse-width modulation signal at same time, so it eliminates the need of additional chip area of another phase signal circuit. In order to upgrade the resolution to 8 bits at clock frequency of 30 MHz, the second part of this thesis proposed the segmented delay-line based DPWM using TSMC 90-nm CMOS process. The architecture uses a two-stage delay line to reduce the number of delay cells to save the chip size. For 8-bit resolution and 30-MHz clock frequency, the INL is measured to be 15.9 ~ -20.2 LSB, and DNL is 22 ~ -20.3 LSB. When 6-bit resolution and 150-MHz clock frequency, the INL is measured to be 1.29 ~ -0.94 LSB, and DNL is 1.05 ~ -0.62 LSB.