互補式金氧半導體射頻時脈產生器之設計

Abstract

在有線或是無線的通訊系統中，隨著操作頻率越來越高。作為系統的表準時脈的高速頻率合成器，就扮演一個重要的角色。然而要實現一個具有低功耗、低相位雜訊以及維持全頻帶穩定的頻率合成器，是有許多困難需要克服的。為了舒緩以上的問題，如何對於各種電路特性做最佳的取捨是重要的議題。 在系統中作為系統標準頻率的時脈產生器，最簡單的方式就是一個振盪器就可以完成。而振盪器電路最重要的指標效能-相位雜訊，對於高階的通訊系統要求十分嚴格。為了讓電路本身的特性不會受到外界雜訊干擾而劣化，我們設計了一個穩壓電路來排除這樣的問題。壓控振盪器在低頻率位移的相位雜訊會受到製成的限制，於是我們便進一步製作了鎖相迴路電路，藉由迴路濾波器的功能來達到近頻雜訊的濾除。 第二章我們介紹了穩壓電路的原理以及特性，第三章我們呈現了內建穩壓電路的壓控振盪器，壓控振盪器使用變壓器回授的技巧來增加電感的品質因素來達到較佳的相位雜訊效能。除此之外，為了增加壓控振盪器對於外界雜訊免疫的能力，設計了一個穩壓電路達到這個效果。此電路的整體功耗為23.4 mW，相位雜訊的特性為-112dBc/Hz在1MHz 位移下。 第四章呈現了兩個K頻段的時脈產生器電路。分別為低功耗低雜訊鎖相迴路以及頻率合成器。其中鎖相迴路，採用了第三章所提到的變壓器迴授的壓控震盪器來達到低相位雜訊。此外我們也使用了疊接式的除頻器，達到低功耗。這個電路的功耗為25mW，相位雜訊的效能達到了-90 dBc/Hz在1MHz位移下，參考頻率突波為 -58dBc。在近期的無線通訊系統中，只用單一個收發機來達到多頻帶的使用已經變成一個趨勢。基於成本考量只使用一個寬頻的頻率合成器，避免使用過多的鎖相迴路，是十分具有吸引力的。基於先前的鎖相迴路設計經驗，我們進一步設計了頻率合成器。此頻率合成器達到了19.2GHz 到20.6 GHz的頻率合成範圍，電路的功耗為 38.6 mW，相位雜訊特性為-76 dBc在1MHz位移下, 參考突波為-40 dBc。

As the operating frequency becomes higher, high-speed frequency synthesizer plays an important role in wire line or wireless communication systems. However, to realize a high-speed frequency synthesizer while achieving low power, low phase and full-band stability at the same time has considerable difficulty. To alleviate the above problems, a good tradeoff between them has to be made. The integrated system needs a clock source to be standard frequency, and a simple way to generate a clock source is to integrate oscillators in system. In high order communication system, it has a strict specification in VCO index performance. Thus, we design a regulator to prevent the noise from outside to deteriorate phase noise performance. However, as the close in phase noise of VCO is dominate by the device itself, we design a phase-locked loop to alleviate this problem. We filter the in band noise by the loop filter in the phase-locked loop. In Chapter 2 , we introduce the design theory and the characteristics of a regulator. In Chapter 3, we present a supply regulated voltage-controlled oscillator(VCO), using transformer feedback technique to enhance the quality factor of the inductor and then achieve a better phase noise. We design a regulator to reject the supply noise additionally. This design consumes 23.4 mW power, and achieves phase noise of -112dBc/Hz at 1 MHz offset. In chapter 4, we present two K-band clock generators. One is a low power, low phase noise phase-locked loop, this work employed TF-VCO mentioned in chapter 3 to alleviate noise issue. Besides, we use cascoded divider to achieve low power. This work consumes 25 mW and achieves phase noise of -90 dBc/Hz at 1MHz offset, reference spur is -58 dBc. Multi-band support by only one transceiver chip becomes a trend in recent wireless communication circuit design. It is highly desirable to have a single wide operation frequency synthesizer, preventing using too many PLL in the multi-band RF transceivers for cost consideration. Based on the previous design, we extend it to be a frequency synthesizer. This work achieves frequency range from 19.2 GHz to 20.6 GHz, consumes 38.6 mW power, phase noise of -76 dBc/Hz at 1MHz offset, and reference spur -40 dBc.