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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李致毅(Jri Lee) | |
| dc.contributor.author | Jhih-Yu Jiang | en |
| dc.contributor.author | 姜致宇 | zh_TW |
| dc.date.accessioned | 2021-06-07T17:56:24Z | - |
| dc.date.copyright | 2012-08-17 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-08-14 | |
| dc.identifier.citation | [1] T. Ruotsalainen et al., “A Wide Dynamic Range Receiver Channel for a Pulsed
Time-of-Flight Laser Radar,” IEEE J. Solid-State Circuits, vol. 36, no. 8, pp. 1228-1238, Aug. 2001. [2] S. Kurtti and J. Kostamovaara, “Laser Radar Receiver Channel With Timing Detector Based on Front End Unipolar-to-Bipolar Pulse Shaping,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 835-847, March 2009. [3] Laser Technology, Inc., “Laser Speed Detection System Operator’s Manual,” 1990. [4] Greenhatch Group. [Online]. Available: http://www.greenhatch-group.co.uk/3D-Laser-Scanning [5] IEEE P802.3ba 40Gb/s and 100Gb/s Ethernet Task Force. [Online]. Available: http://www.ieee802.org/3/ba/ [6] Universal Serial Bus. [Online]. Available: http://www.usb.org/ [7] Serial ATA. [Online]. Available: http://www.sata-io.org/ [8] PCI-SIG. [Online]. Available: http://www.pcisig.com/ [9] Behzad Razavi, Design of Integrated Circuits for Optical Communications, First Ed., New York: McGRAW-HILL, 2003. [10] W.-L. Lee et al., “A Laser Ranging Radar Transceiver with Modulated Evaluation Clock in 65-nm CMOS Technology,” Digest of Symposium on VLSI Circuits, pp. 286-287, June 2011. [11] P. Palojarvi, et al., “A 250-MHz BiCMOS Receiver Channel With Leading Edge Timing Discriminator for a Pulsed Time-of-Flight Laser Rangefinder,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1341-1349, June. 2005. [12] J. Nissinen et al., “Integrated Receiver Including Both Receiver Channel and TDC for a Pulsed Time-of-Flight Laser Rangefinder With cm-Level Accuracy,” IEEE J. Solid-State Circuits, vol. 44, no. 5, pp.1486-1497, May 2009. [13] R. Ziemer and W. Tranter, Principles of Communications, 2nd Ed. Boston, MA: Houghton Mifflin, 1985. [14] Y. Lien and J. Lee, “A 6-b 1-GS/s 30-mW ADC in 90-nm CMOS Technology,” IEEE Asian Solid-State Circuits Conf. Tech. Papers, pp. 45-48, Nov. 2008. [15] LASER COMPONENTS. [Online]. Available: http://www.lasercomponents.com/ [16] Edmund. [Online]. Available: http://www.edmundoptics.com/ [17] C. Cole et al., “100 GbE-Optical LAN Technologies,” IEEE Commun. Mag., vol. 45,pp. 12-19, Dec. 2007. [18] J. J. O’Reilly, “Series-parallel generation of m-sequences,” Radio Electron. Eng., 1975. [19] J. Yuan et al., “New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings,” IEEE J. Solid-State Circuits, vol. 32, pp. 62-69, Jan. 1997. [20] S. Pellerano et al., “A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC -Based All-Digital Spur Calibration in 45-nm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3422-3433, Dec. 2009. [21] C.-W. Lo and H. C. Luong, “A 1.5-V 900-MHz Monolithic CMOS Fast-Switching Frequency Synthesizer for Wireless Applications,” IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 459-470, Apr. 2002. [22] Troy Beukema et al., 'A 6.4-Gb/s CMOS SerDes Core With Feed-Forward and Decision-Feedback Equalization,” IEEE J. Solid-State Circuits, vol. 40, no.12, pp. 2633-2645, Dec. 2005. [23] John F. Bulzacchelli et al., “A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2885-2900, Dec. 2006. [24] Huaide Wang et al., 'A 21-Gb/s 87-mW Transceiver with FFE/DFE/Linear Equalizer in 65-nm CMOS Technology,' Digest of Symposium on VLSI Circuits, pp. 50-51, June 2009. [25] K. Wu and Jri Lee, “A 2 × 25-Gb/s Receiver With 2:5 DMUX for 100-Gb/s Ethernet, “IEEE J. Solid-State Circuits, vol. 45, pp. 2421-2432, Nov. 2010 [26] Charles R. Hogge, Jr., 'A Self Correcting Clock Recovery Circuit,” IEEE Transaction on Election Device, vol. 32, no. 12, pp. 2704-2706, Dec. 1985. [27] J. D. H. Alexander, “Clock Recovery From Random Binary Signal,” Electronics Letters, vol. 11, pp. 541-542, Oct. 1975. [28] Jri Lee et al, “Modeling of Jitter in Bang-Bang Clock and Data Recovery Circuits,”Custom Integrated Circuits Conference Proceedings, pp. 711-714, Sept. 2003. [29] Jri Lee, and K. Wu, 'A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition,' IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3590-3602, Dec. 2009. [30] A. Pottbacker et al., “A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1747-1751, Dec. 1992. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15957 | - |
| dc.description.abstract | 本論文中，提出了兩種以65奈米互補式金氧半製程製作的應用於光通訊的傳輸機，其包括一應用於雷射測距雷達之前端電路以及一應用於100-Gb/s乙太網路的2×25-Gb/s串行器/解串行器。
在雷射測距雷達中，其前端電路採用一雙位準的偵測方式來消除測距雷達本身的飄移誤差，並且使用了一校正電路來修正電壓偏移。此前端電路、光模組和時間數位轉換器可整合成一完整測距雷達，此測距雷達亦採用了一種調變頻率的演算法來達成更高的精確度，最後可達到小於3毫米的精確度，功耗為50毫瓦。 在2×25-Gb/s串行器/解串行器，串行器內包含了2^7-1偽二進位隨機訊號產生器、多工器以及前饋等化器，解串行器則有限幅放大器、資料時脈回復電路以及解多工器。此外，串行器和解串行器分別有其各自的時脈產生器。此組晶片經測試可達到小於小於10^-12的位元誤碼率，而串行器和解串行器則分別消耗300毫瓦和520毫瓦之功率。 | zh_TW |
| dc.description.abstract | In this thesis, two different kinds of transceivers for optical communication have been proposed, including a front-end circuit used in laser ranging radar and a 2×25-Gb/s
serializer/desrializer (SERDES) for 100-Gb/s Ethernet. They are both implemented in 65-nm CMOS technology. In laser ranging radar, the front-end circuit adopts two-threshold method to eliminate walk error of the radar, and uses a calibration circuit to correct the voltage offset . The front-end circuit, optical component, and time-to-digital converter (TDC)can be integrated to a complete ranging radar, and the radar utilizes a modulated clock algorithm to improve accuracy. Finally, it achieves a accuracy of less than 3 mm and consumes 50 mW. In 2×25-Gb/s SERDES, 2^7-1 pseudo random binary sequence (PRBS) generator, multiplexer (MUX), and feed-forward equalizer (FFE) are implemented in serializer. The deserializer includes limiting amplifier, clock and data recovery (CDR) circuit, and demultiplexer (DMUX). Furthermore, serializer and desrializer have their respective clock generators. The chip-set can achieves BER < 10^-12, and consumes 300 mW and 520 mW in serializer and deserilizer, respectively. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-07T17:56:24Z (GMT). No. of bitstreams: 1 ntu-101-R98943005-1.pdf: 8966300 bytes, checksum: bf3b57d9233777074903ed5fea4a2f1b (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | 口試委員審定書(中文) I
口試委員審定書(英文) II 摘要 III ABSTRACT IV CONTENTS V LIST OF FIGURES VII LIST OF TABLES X Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Front-End Circuit used in Laser Ranging Radar Transceiver with Modulated Evaluation Clock 3 2.1 Basic Principle of Time-of-Flight Measurement 3 2.2 Radar Architecture 4 2.3 Building Block 6 2.3.1 Pulse Detector 6 2.3.2 TIA and Preamplifier 8 2.3.3 Comparator and Calibration Unit 9 2.3.4 Threshold Generator 13 2.4 Measurement Result 14 Chapter 3 A 2×25-Gb/s SERDES for 100-Gb/s Ethernet Application 22 3.1 System Architecture of 100-Gb/s Ethernet 22 3.2 Serializer Architecture 23 3.2 3.2.1 PRBS Generator 24 3.2 3.2.2 Two-Step Conversion MUX 26 3.2.3 Clock Generator 28 3.2.4 FFE 30 3.3 Deserializer Architecture 32 3.3.1 Limiting Amplifier 33 3.3.2 CDR Circuit 34 3.3.3 2-to-5 DMUX 37 3.3.4 Clock Generator 40 3.4 Measurement Result 43 3.4.1 Serializer Measurement 43 3.4.2 Deserializer Measurement 47 3.4.3 Performance Summary 53 Chapter 4 Conclusion 55 Bibliography 56 | |
| dc.language.iso | en | |
| dc.subject | 解串行器 | zh_TW |
| dc.subject | 光通訊 | zh_TW |
| dc.subject | 乙太網路 | zh_TW |
| dc.subject | 雷射測距 | zh_TW |
| dc.subject | 串行器 | zh_TW |
| dc.subject | 飄移誤差 | zh_TW |
| dc.subject | Deserializer | en |
| dc.subject | Optical Communication | en |
| dc.subject | Laser Ranging | en |
| dc.subject | Walk Error | en |
| dc.subject | Serializer | en |
| dc.subject | Ethernet | en |
| dc.title | 以65-nm CMOS製程製作應用於光通訊之收發器 | zh_TW |
| dc.title | Transceivers for Optical Communication in 65-nm CMOS Technology | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 呂學士(Shey-Shi Lu),盧信嘉(Hsin-Chia Lu) | |
| dc.subject.keyword | 雷射測距,飄移誤差,串行器,解串行器,乙太網路,光通訊, | zh_TW |
| dc.subject.keyword | Laser Ranging,Walk Error,Serializer,Deserializer,Ethernet,Optical Communication, | en |
| dc.relation.page | 58 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2012-08-15 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
| ntu-101-1.pdf 未授權公開取用 | 8.76 MB | Adobe PDF |
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