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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳怡然(Yi-Jan Chen) | |
| dc.contributor.author | Chi-Wei Cheng | en |
| dc.contributor.author | 鄭治葳 | zh_TW |
| dc.date.accessioned | 2021-06-07T17:56:00Z | - |
| dc.date.copyright | 2012-08-17 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-08-14 | |
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Theory Tech., vol. 57, no. 4, pp. 919-927, Apr. 2009. [6] Q. Nan, X. Yang, C. Baoyong, X. Yang, Y. Xiaobao, Z. Xing, and W. Zhihua, 'A dual-channel GPS/Compass/Galileo/GLONASS reconfigurable GNSS receiver in 65nm CMOS,' in Custom Integrated Circuits Conference (CICC), 2011 IEEE, 2011, pp. 1-4. [7] J. M. Samper, R. B. Perez, and J. M. Lagunilla, GPS & Galileo: Dual RF Front-end Receiver and Design, Fabrication, and Test, New York: McGraw-Hill, 2009. [8] D. K. Shaeffer and T. H. Lee, The Design and Implementation of Low-Power CMOS Radio Receivers, New York: Kluwer Academic Publishers, 2002. [9] H. Ta-Tao and K. Chien-Nan, 'Low power 8-GHz ultra-wideband active balun,' in Silicon Monolithic Integrated Circuits in RF Systems, 2006. Digest of Papers. 2006 Topical Meeting on, 2006, p. 4 pp. [10] M. Soyuer and R. G. Meyer, 'Frequency limitations of a conventional phase-frequency detector,' IEEE J. Solid-State Circuits, vol. 25, no. 4, pp. 1019-1022, Apr. 1990. [11] X. Yang, C. Baoyong, Y. Xiaobao, Q. Nan, P. Chiang, and W. Zhihua, 'Power-Scalable, Complex Bandpass/Low-Pass Filter With I/Q Imbalance Calibration for a Multimode GNSS Receiver,' Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 59, pp. 30-34, 2012. [12] N. K. Yanduru and K. M. Low, 'A highly integrated GPS front-end for cellular applications in 90nm CMOS,' in Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software, 2008 IEEE Dallas, 2008, pp. 1-4. [13] K. Woonyun, Y. Jinhyuck, S. Heeseon, Y. Sung-Gi, C. Wooseung, and P. Byeong-Ha, 'A dual-b and RF front-end of direct conversion receiver for wireless CDMA cellular phones with GPS capability,' IEEE Trans. Microw. Theory Tech., vol. 54, no. 5, pp. 2098-2105, May 2006. [14] V. D. Torre, M. Conta, R. Chokkalingam, G. Cusmai, P. Rossi, and F. Svelto, 'A 20 mW 3.24 mm2 Fully Integrated GPS Radio for Location Based Services,' IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 602-612, Mar. 2007. [15] A. R. Shahani, D. K. Shaeffer, and T. H. Lee, 'A 12-mW wide dynamic range CMOS front-end for a portable GPS receiver,' IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 2061-2070, Dec. 1997. [16] G. Montagna, G. Gramegna, I. Bietti, M. Franciotta, A. Baschirotto, P. De Vita, R. Pelleriti, M. Paparo, and R. Castello, 'A 35-mW 3.6-mm2 fully integrated 0.18-μm CMOS GPS radio,' IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1163-1171, Jul. 2003. [17] J. G. Maneatis, 'Low-jitter process-independent DLL and PLL based on self-biased techniques,' IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, Nov. 1996. [18] L. Kyoohyun, L. Sang-Hoon, M. Sunki, S. Ock, H. Myung-Woon, L. Chang-Hee, K. Kyung-Lok, and H. Sangwoo, 'A Fully Integrated Direct-Conversion Receiver for CDMA and GPS Applications,' IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2408-2416, Nov. 2006. [19] C. Kuang-Wei, K. Natarajan, and D. J. Allstot, 'A Current Reuse Quadrature GPS Receiver in 0.13 um CMOS,' IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 510-523, Mar. 2010. [20] L. Joonsuk and K. Beomsup, 'A low-noise fast-lock phase-locked loop with adaptive bandwidth control,' IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1137-1145, Aug. 2000. [21] G. Gramegna, P. G. Mattos, M. Losi, S. Das, M. Franciotta, N. G. Bellantone, M. Vaiana, V. Mandara, and M. Paparo, 'A 56-mW 23-mm2 single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1-mm2 radio,' IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 540-551, Mar. 2006. [22] J. Craninckx and M. S. J. Steyaert, 'A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-um CMOS,' IEEE J. Solid-State Circuits vol. 31, no. 7, pp. 890-897, Jul. 1996. [23] Qizheng Gu, RF System Design of Transceivers for Wireless Communications, New York: Springer, 2005. [24] Behzad Razavi, RF Microelectronicst, Upper Saddle River, NJ: Prentice Hall PTR, 1998. [25] Thomas H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd ed., Cambridge: Cambridge University Press, UK, 2004. [26] Bernhard Hofmann-Wellenhof, Herbert Lichtenegger, Elmar Wasle, GNSS – Global Navigation Satellite Systems GPS, GLONASS, Galileo, and more, idge: New York: Springer, 2008. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15942 | - |
| dc.description.abstract | 本論文提出一個應用在多標準全球衛星導航(GNSS)接收機前端電路架構用來同時接收L1頻段的衛星導航訊號，包含美國的GPS、俄國的GLONASS、以及歐盟的Galileo。由於未來全球衛星導航系統將不是只有一種規格，而且各個規格有各自的軌道安排考量，預期同時接收多種規格的衛星導航訊號並交由後端數位訊號處理(DSP)綜合定位將會成為未來的趨勢。根據鏡像消除接收機的原理，利用一個頻率位於1588.57 MHz的本地震盪(LO)訊號，將位於1575.42 MHz的GPS及Galileo訊號和位於1597.5515 MHz 到 1605.886 MHz的GLOANSS訊號互相視為一組鏡像訊號，由於利用I/Q相位降頻時會讓本地震盪頻率兩端的射頻(RF)訊號擁有不同的訊號相位關係，透過多相位濾波器便可選擇出想要的頻率訊號，並且在輸出端被區分開來。不同於現行的接收機架構，此架構只利用一組接收機前端電路，如此可以節省晶片製作上的成本，並且有效的降低功率消耗。
我們採用了TSMC 90-nm CMOS製程設計並實現了一個全積體化的接收機電路，包括了低雜訊放大器(LNA)、 被動式混波器(Passive Mixer)、多相位濾波器(Polyphase Filter)、以及一個頻率合成器(Frequency Synthesizer)，此電路為低中頻的架構，輸出頻率分別為GPS/Galileo的13.15 MHz和GLONASS的8.9815 MHz到17.316 MHz，並且提供20.5dB的鏡像消除，而在1V的電源供應器之下，功率消耗為15.79 mW、晶片面積為1.536 mm2 | zh_TW |
| dc.description.abstract | This thesis introduces a multi-standard receiver architecture aiming to simultaneously receive the L1 band Global Navigation Satellite System (GNSS) signals including GPS, GLONASS and Galileo. These multi-standard signals can be computed by the back-end DSP to provide a more robust navigation when GLONASS and Galileo become fully operational in the near future. Based on the principle of image-reject receiver with a LO frequency at 1588.57 MHz, the signals of GPS/Galileo at 1575.42 MHz and GLONASS at 1597.5515 MHz to 1605.886 MHz can be viewed as a pair of mirrored signals. From the differences in the phase relationship caused by I/Q down-converting signals in the double-side of LO frequency, we can select the desired output signal by a polyphase filter. This is the part that makes it different from the other multi-standard receiver architecture. Our approach receives three GNSS signals simultaneously with only one receiver chain. Therefore, this architecture provides the benefits of lowering the cost of chip manufacturing and increasing the power efficiency.
For the fabrication, we use TSMC 90-nm CMOS process to design and implement a fully integrated receiver circuit, including a low noise amplifier (LNA), passive mixers, polyphase filters, and a frequency synthesizer. This receiver is based on a low-IF architecture, and the output frequencies are 13.15 MHz for GPS/Galileo and 8.9815 MHz to 17.316 MHz for GLONASS respectively with a 20.14/20.5 dB image reject ratio. The power consumption is 15.79 mW with a 1-V power supply, and the die area is 1.536 mm2. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-07T17:56:00Z (GMT). No. of bitstreams: 1 ntu-101-R97943115-1.pdf: 4602798 bytes, checksum: 96d579db5a2c266f8944536506b853d1 (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | 致謝 ............................................................ i
摘要 ............................................................ iii Abstract ........................................................ v Contents ........................................................ vii List of Figures ................................................. ix List of Tables .................................................. xiii Chapter 1 Introduction .......................................... 1 1.1 Motivation .................................................. 1 1.2 Survey of GNSS Receiver ..................................... 3 1.2.1 A 90-nm CMOS Single-Chip GPS Receiver ..................... 3 1.2.2 A GPS Receiver with Robust Interferer Rejection ........... 5 1.2.3 A GPS Receiver Integrated in a Multimode Receiver.......... 7 1.2.4 An L1/L2 Dual-Band CMOS GPS Receiver ...................... 9 1.2.5 An L1 band Dual-Mode RF Receiver .......................... 11 1.2.6 A Dual-Channel Reconfigurable GNSS Receiver ............... 13 1.3 Thesis Organization ......................................... 15 Chapter 2 Global Navigation Satellite Systems.................... 17 2.1 Overview of GNSS ............................................ 17 2.1.1 GPS (U.S.A) ............................................... 18 2.1.2 GLONASS (Russian) ......................................... 22 2.1.3 Galileo (Europe) .......................................... 24 2.1.4 Compass and QZSS .......................................... 26 2.2 Positioning Principle ....................................... 29 2.2.1 Basic Principle ........................................... 29 2.2.2 Pseudo-range Measurements ................................. 31 2.3 Signal Structure ............................................ 33 2.3.1 Frequency Spectrum ........................................ 33 2.3.2 Modulation Schemes ........................................ 36 Chapter 3 Receiver Front-end System Design ...................... 41 3.1 Survey of Receiver Architectures ............................ 41 3.1.1 Heterodyne Receivers....................................... 41 3.1.2 Homodyne Receiver ......................................... 48 3.1.3 Image Reject Receiver ..................................... 52 3.1.4 Subsampling Receiver ...................................... 57 3.2 Receiver Architecture and Specification ..................... 59 3.2.1 The Concept of Proposed Architecture ...................... 59 3.2.2 Polyphase Filter........................................... 62 3.2.3 The Issues of Receiver Design ............................. 64 3.3 Behavior Simulation and Circuit Specification ............... 69 3.3.1 Behavior Simulation ....................................... 69 3.3.2 Image Rejection Consideration ............................. 71 3.3.3 Receiver Specification .................................... 74 Chapter 4 Receiver Front-end Circuit Design ..................... 77 4.1 Low Noise Amplifier and Active Balun ........................ 78 4.2 Passive Mixer ............................................... 83 4.3 Variable Gain Amplifier ..................................... 85 4.4 Polyphase Filter ............................................ 87 4.5 Frequency Synthesizer ....................................... 89 4.5.1 Architecture of Frequency Synthesizer ..................... 89 4.5.2 PFD........................................................ 90 4.5.3 Charge Pump and Loop Filter ............................... 91 4.5.4 Voltage Control Oscillator ................................ 93 4.5.5 Frequency Divider ......................................... 96 4.5.6 Simulation Results of Frequency Synthesizer ............... 98 4.6 Simulation Results of Receiver Front-end .................... 100 Chapter 5 Experimental Results .................................. 103 5.1 Measurement Environment and Setup ........................... 104 5.2 Measurement Results ......................................... 107 5.3 Summary ..................................................... 112 Chapter 6 Conclusion ............................................ 115 Reference ....................................................... 117 | |
| dc.language.iso | en | |
| dc.subject | 多相位濾波器 | zh_TW |
| dc.subject | 全球衛星導航 | zh_TW |
| dc.subject | 接收機 | zh_TW |
| dc.subject | 鏡相消除 | zh_TW |
| dc.subject | 低中頻 | zh_TW |
| dc.subject | image reject | en |
| dc.subject | polyphase filter | en |
| dc.subject | low-IF | en |
| dc.subject | GNSS | en |
| dc.subject | receiver | en |
| dc.title | 使用90奈米CMOS之多標準全球衛星導航系統接收機前端電路 | zh_TW |
| dc.title | A 90-nm CMOS Multi-standard GNSS Receiver Front-end | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 邱煥凱(Hwann-Kaeo Chiou),陳筱青(Hsiao-Chin Chen),蔡政翰(Jeng-Han Tsai) | |
| dc.subject.keyword | 全球衛星導航,接收機,鏡相消除,低中頻,多相位濾波器, | zh_TW |
| dc.subject.keyword | GNSS,receiver,image reject,low-IF,polyphase filter, | en |
| dc.relation.page | 120 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2012-08-15 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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