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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉深淵 | |
| dc.contributor.author | Shih-Yuan Kao | en |
| dc.contributor.author | 高世源 | zh_TW |
| dc.date.accessioned | 2021-06-07T17:54:58Z | - |
| dc.date.copyright | 2012-08-17 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-08-16 | |
| dc.identifier.citation | Bibliography
[1] F. Herzel and B. Razavi, “A study of oscillator jitter due to supply and substrate noise,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 46, no. 1, pp. 56–62, Jan. 1999. [2] P. Heydari, “Analysis of the PLL jitter due to power/ground and substrate noise,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 12, pp. 2404–2416, Dec. 2004. [3] S. Sidiropoulos, D. Liu, J. Kim, G. Wei, and M. Horowitz, “Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2000, pp. 124-127. [4] C. Lee, K. McClellan, and J. Choma, “A supply-noise-insensitive CMOS PLL with a voltage regulator using DC-DC capacitive converter,” IEEE J. Solid-State Circuits, vol. 36, no.10, pp. 1453–1463, Oct. 2001. [5] E. Alon, J. Kim, S. Pamarti, K. Chnag, and M. Horowitz, “Replica compensated linear regulators for supply-regulated phase-locked loops,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 413–424, Feb. 2006. [6] M. Brownlee, P. Hanumolu, K. Mayaram, and U. Moon, “A 0.5 to 2.5 GHz PLL with fully differential supply-regulated tuning,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2720–2728, Dec. 2006. [7] A. Arakali, S. Gondi, and P. Hanumolu, “A 0.5-to-2.5 GHz supply-regulated PLL with noise sensitivity of -28 dB,” in Proc. IEEE Custom Integr. Circuits Conf., Sept. 2008, pp. 443–446. [8] P.-H. Hsieh, J. Maxey, and C.-K. K. Yang, “Minimizing the supply sensitivity of CMOS ring oscillator by jointly biasing the supply and control voltage,” in Proc. IEEE Custom Integr. Circuits Conf., Sept. 2008, pp.531-534. [9] I. Hwang, C. Kim, and S. Kang, “A CMOS self-regulating VCO with low supply sensitivity,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 42–48, Jan. 2004. [10] M. Mansuri and C. Yang, “A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation,” IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1804–1812, Nov. 2003. [11] T. Wu, K. Mayaram, and U. Moon, “An on-chip calibration technique for reducing supply voltage sensitivity in ring oscillators,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 775–783, Apr. 2007. [12] M. Popovich, M. Sotman, A. Kolodny, and E. G. Friedman, “Effective radii of on-chip decoupling capacitors,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 7, pp. 894-906, Jul. 2008. [13] J. Gu, R. Harjani, and C. H. Kim, “Design and implementation of active decoupling capacitor circuits for power supply regulation in digital ICs,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 2, pp. 292-301, Feb. 2009. [14] S. Pant and D. Blaauw, “A charge-injection-based active-decoupling technique for inductive-supply-noise suppression,” in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2008, pp. 416-417. [15] R. Farjad-Rad, C.-K. Ken Yang, M. A. Horowitz, and T. H. Lee, “A 0.4-µm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter,” IEEE J. Solid-State Circuits, vol. 34, no.5, pp.580–585, May 1999. [16] J.-R. Schrader, E. A. M. Klumperink, J. L. Visschers, and B. Nauta, “Pulse-width modulation pre-emphasis applied in a wireline transmitter, achieving 33 dB loss compensation at 5-Gb/s in 0.13-μm CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 990–999, April 2006. [17] J. F. Buckwalter, M. Meghelli, D. J. Friedman, and A. Hajimiri, “Phase and amplitude pre-emphasis techniques for low-power serial links,” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1391–1399, June 2006. [18] K.-L. Jackie Wong, A. Rylyakov, and C.-K. Ken Yang, “A 5-mW 6-Gb/s quarter-rate sampling receiver with a 2-tap DFE using soft decisions,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 881–888, April 2007. [19] E.-H. Chen, J. Ren, B. Leibowitz, H.-C. Lee, Q. Lin, K. Oh, F. Lambrecht, V. Stojanovic, J. Zerbe, and C.-K. K. Yang, “Near-optimal equalizer and timing adaptation for I/O links using a BER-based metric,” IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 2144–2156, Sep. 2008. [20] K.-L. Jackie Wong, E.-H. Chen, and C.-K. Ken Yang, “Edge and data adaptive equalization of serial-link transceivers,” IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 2157–2169, Sep. 2008. [21] H. Wang, C.-C. Lee, A.-M. Lee, and J. Lee, “A 21-Gb/s 87-mW transceiver with FFE/DFE/linear equalizer in 65-nm CMOS technology,” in Proc. Symp. VLSI Circuits, Jun. 2009, pp. 50–51. [22] A. Ho, V. Stojanovic, F. Chen, C. Werner, G. Tsang, E. Alon, R. Kollipara, J. Zerbe, and M. A. Horowitz, “Common-mode backchannel signaling system for differential high-speed links,” in Proc. Symp. VLSI Circuits, Jun. 2004, pp. 352–355. [23] K. Yamaguchi, K. Sunaga, S. Kaeriyama, T. Nedachi, M. Takamiya, K. Nose, Y. Nakagawa, M. Sugawara, and M. Fukaishi, “12Gb/s duobinary signaling with x2 oversampled edge equalization,” in proc. IEEE ISSCC, Feb. 2005, pp.70-71. [24] Y. Tomita, H. Tamura, M. Kibune, J. Ogawa, K. Gotoh, and T. Kuroda, “A 20Gb/s bidirectional transceiver using a resistor-transconductor hybrid,” in proc. IEEE ISSCC, Feb. 2006, pp.518-519. [25] J. Lee and H. Wang, “A 20Gb/s broadband transmitter with auto-configuration technique,” in proc. IEEE ISSCC, Feb. 2007, pp.444-445. [26] D. Tonietto, J. Hogeboon, E. Bensoudane, S. Sadeghi, H. Khor, and P. Krotnev, “A 7.5Gb/s transmitter with self-adaptive FIR,” in proc. Symp. VLSI Circuits, Jun. 2008, pp. 198–199. [27] Video Electronics Standards Association, “VESA Displayport Standard Version 1.1,” Mar. 19 2007. [28] R. Farjad-Rad, C.-K. Ken Yang, M. A. Horowitz, and T. H. Lee, “A 0.4-µm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter,” IEEE J. Solid-State Circuits, vol. 34, no.5, pp.580–585, May 1999. [29] R. A. Aroca and S. P. Voinigescu, “A large swing, 40-Gb/s SiGe BiCMOS driver with adjustable pre-emphasis for data transmission over 75 Ω coaxial cable,” IEEE J. Solid-State Circuits, vol. 43, no. 10, pp. 2177–2186, Oct. 2008. [30] P. Westergaard, T. O. Dickson, and S. P. Voinigescu, “A 1.5V 20/30 Gb/s CMOS backplane driver with digital pre-emphasis,” in Proc. IEEE Custom Integr. Circuits Conf., Oct. 2004, pp. 23–26. [31] H. Cheng, F. A. Musa, and A. C. Carusone, “A 32/16-Gb/s dual-mode pulsewidth modulation pre-emphasis(PWM-PE) transmitter with 30-dB loss compensation using a high-speed CML design methodology,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 8, pp. 1794–1806, Aug. 2009. [32] A. Momtaz and M. M. Green, “An 80 mW 40 Gb/s 7-tap T/2-spaced FFE in 65 nm CMOS,” in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 2009, pp.364-365. [33] J. Lee and H. Wang, “A 20Gb/s broadband transmitter with auto-configuration technique,” in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp.444-445. [34] J. F. Bulzacchelli, M. Meghelli, S. V. Rylov, W. Rhee, A. V. Rylyakov, H. A. Ainspan, B. D. Parker, M. P. Beakes, A. Chung, T. J. Beukema, P. K. Pepeljugoski, L. Shan, Y. H. Kwark, S. Gowda, and D. J. Friedman, “A 10-Gb/s 5-tap DFE/4-tap FFE transceiver in 90-nm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2885–2900, Dec. 2006. [35] A. Garg, A. C. Carusone, and S. P. Voinigescu, “A 1-tap 40-Gb/s look-ahead decision feedback equalizer in 0.18-µm SiGe BiCMOS technology,” IEEE J. Solid-State Circuits, vol. 41, no. 10, pp. 2224–2232, Oct. 2006. [36] C.-L. Hsieh, and S.-I. Liu, “A 40Gb/s decision feedback equalizer using back-gate feedback technique,” in Proc. Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2009, pp. 218–219. [37] H. Wang, C.-C. Lee, A.-M. Lee, and J. Lee, “A 21-Gb/s 87-mW transceiver with FFE/DFE/linear equalizer in 65-nm CMOS technology,” in Proc. Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2009, pp. 50–51. [38] C.-F. Liao and S.-I. Liu, “A 40Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery,” IEEE J. Solid-State Circuits, vol. 43, no. 11, pp. 2492–2502, Nov. 2008. [39] V. Stojanovic, A. Ho, B. W. Garlepp, F. Chen, J. Wei, G. Tsang, E. Alon, R. T. Kollipara, C. W. Werner, J. L. Zerbe, and M. A. Horowitz, “Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery,” IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 1012–1026, Apr. 2005. [40] S. Gondi and B. Razavi, “Equalization and clock and data recovery techniques for 10-Gb/s CMOS serial-link receivers,” IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1999–2011, Sep. 2007. [41] C. Pelard, E. Gebara, A. J. Kim, M. G. Vrazel, F. Bien, Y. Hur, M. Maeng, S. Chandramouli, C. Chun, S. Bajekal, S. E. Ralph, B. Schmukler, V. M. Hietala, and J. Laskar, “Realization of multigigabit channel equalization and crosstalk cancellation integrated circuits,” IEEE J. Solid-State Circuits, vol. 39, no. 10, pp. 1659–1670, Oct. 2004. [42] Y. Hur, M. Maeng, C. Chun, F. Bien, H. Kim, S. Chandramouli, E. Gebara, and J. Laskar, “Equalization and near-end crosstalk (NEXT) noise cancellation for 20-Gb/s 4-PAM backplane serial I/O interconnections,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 1, pp. 246–255, Jan. 2005. [43] J.-H. Lu and S.-I. Liu, “A merged CMOS digital near-end crosstalk canceller and analog equalizer for multi-lane serial-link receivers,” IEEE J. Solid-State Circuits, vol. 45, no. 2, pp. 433–446, Feb. 2010. [44] J. Buckwalter, B. Analui, and A. Hajimiri, “Data-dependent jitter and crosstalk-induced bounded uncorrelated jitter in copper interconnects,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2004, pp. 1627–1630. [45] K. Lee, H.-B. Lee, H.-K. Jung, J.-Y. Sim, and H.-J. Park, “A serpentine guard trace to reduce the far-end crosstalk voltage and the crosstalk induced timing jitter of parallel microstrip lines,” IEEE Trans. Adv. Packag., vol. 31, no. 4, pp. 809–817, Nov. 2008. [46] K. Lee, H.-K. Jung, H.-J. Chi, H.-J. Kwon, J.-Y. Sim, and H.-J. Park, “Serpentine microstrip lines with zero far-end crosstalk for parallel high-speed DRAM interfaces,” IEEE Trans. Adv. Packag., vol. 33, no. 2, pp. 552–558, May 2010. [47] K. Lee, H.-K. Jung, J.-Y. Sim, and H.-J. Park, “Reduction of transient far-end crosstalk voltage and jitter in DIMM connectors for DRAM interface,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 1, pp. 15–17, Jan. 2009. [48] J. F. Buckwalter and A. Hajimiri, “Cancellation of crosstalk-induced jitter,” IEEE J. Solid-State Circuits, vol. 41, no.3, pp.621–632, Mar. 2006. [49] H.-K. Jung, K. Lee, J.-S. Kim, J.-J. Lee, J.-Y. Sim, and H.-J. Park, “A 4 Gb/s 3-bit parallel transmitter with the crosstalk-induced jitter compensation using TX data timing control,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 2891–2900, Nov. 2009. [50] K.-J. Sham and R. Harjani, “I/O staggering for low-power jitter reduction,” in Proc. IEEE Eur. Microw. Conf., Oct. 2008, pp. 1226-1229. [51] K.-I. Oh, L.-S. Kim, K.-I. Park, Y.-H. Jun, J. S. Choi, and K. Kim, “A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme,” IEEE J. Solid-State Circuits, vol. 44, no.8, pp.2222–2232, Aug. 2009. [52] J. L. Zerbe, P. S. Chau, C. W. Werner, W. F. Stonecypher, H. J. Liaw, G. J. Yeh, T. P. Thrush, S. C. Best, K. S. Donnelly, “A 2Gb/s/pin 4-PAM parallel bus interface with transmit crosstalk cancellation, equalization, and integrating receivers,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2001, pp. 66–67. [53] H.-K. Jung, S.-M. Lee, J.-Y. Sim, and H.-J. Park, “A slew-rate controlled transmitter to compensate for the crosstalk-induced jitter of coupled microstrip lines,” in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2010, pp.1-4. [54] J.-H. Bae, Y.-S. Sohn, S.-J. Bae, K.-I. Park, J.-S. Choi, Y.-H. Jun, J.-Y. Sim, and H.-J. Park, “A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel,” in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2010, pp. 1-4. [55] S.-J. Bae, Y.-S. Sohn, T.-Y. Oh, S.-H. Kim, Y.-S. Yang, D.-H. Kim, S.-H. Kwak, H.-S. Seol, C.-H. Shin, M.-S. Park, G.-H. Han, B.-C. Kim, Y.-K. Cho, H.-R. Kim, S.-Y. Doo, Y.-S. Kim, D.-S. Kang, Y.-R. Choi, S.-Y. Bang, S.-Y. Park, Y.-J. Shin, G.-S. Moon, C.-G. Park, W.-S. Kim, H.-J. Yang, J.-D. Lim, K.-I. Park, J. S. Choi, and Y.-H. Jun, “A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 498–499. [56] M. H. Nazari and A. Emami-Neyestanak, “A 15Gb/s 0.5mW/Gb/s 2-tap DFE receiver with far-end crosstalk cancellation,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 446–447. [57] T. Oh and R. Harjani, “A 6-Gb/s MIMO crosstalk cancellation scheme for high-speed I/Os,” IEEE J. Solid-State Circuits, vol. 46, no.8, pp.1843–1856, Aug. 2011. [58] S.-K. Lee, H. Ha, H.-J. Park, and J.-Y. Sim, “A 5Gb/s single-ended parallel receiver with adaptive FEXT cancellation,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2012, pp. 140–141. [59] W. J. Dally and J. W. Poulton, Digital Systems Engineering. Cambridge, U.K.: Cambridge Univ. Press, 1998. [60] Y.-S. Sohn, J.-C. Lee, H.-J. Park, and S.-I. Cho, “Empirical equations on electrical parameters of coupled microstrip lines for crosstalk estimation in printed circuit board,” IEEE Trans. Adv. Packag., vol. 24, no. 4, pp. 521–527, Nov. 2001. [61] B. Kim, Y. Liu, T. O. Dickson, J. F. Bulzacchelli, and D. J. Friedman, “A 10-Gb/s compact low-power serial I/O with DFE-IIR equalization in 65-nm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no.12, pp.3526–3538, Dec. 2009. [62] Y.-C. Huang and S.-Y. Liu, “A 6Gb/s receiver with 32.7dB adaptive DFE-IIR equalization,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 356–357. [63] T. Toifl, C. Menolfi, M. Ruegg, R. Reutemann, A. Prati, D. Gardellini, M. Brandli, M. Kossel, P. Buchmann, P. A. Francese, and T. Morf, “A 2.6mW/Gbps 12.5Gbps RX with 8-tap switched-cap DFE in 32nm CMOS,” in Proc. Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2011, pp. 210–211. [64] H. Cirit and J. Loinaz, “A 10Gb/s half-UI IIR-tap transmitter in 40nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 448–449. [65] J. F. Buckwalter and A. Hajimiri, “Cancellation of crosstalk-induced jitter,” IEEE J. Solid-State Circuits, vol. 41, no.3, pp.621–632, Mar. 2006. [66] H.-K. Jung, K. Lee, J.-S. Kim, J.-J. Lee, J.-Y. Sim, and H.-J. Park, “A 4 Gb/s 3-bit parallel transmitter with the crosstalk-induced jitter compensation using TX data timing control,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 2891–2900, Nov. 2009. [67] K.-J. Sham and R. Harjani, “I/O staggering for low-power jitter reduction,” in Proc. IEEE Eur. Microw. Conf., Oct. 2008, pp. 1226-1229. [68] K.-I. Oh, L.-S. Kim, K.-I. Park, Y.-H. Jun, J. S. Choi, and K. Kim, “A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme,” IEEE J. Solid-State Circuits, vol. 44, no.8, pp.2222–2232, Aug. 2009. [69] H.-K. Jung, S.-M. Lee, J.-Y. Sim, and H.-J. Park, “A slew-rate controlled transmitter to compensate for the crosstalk-induced jitter of coupled microstrip lines,” in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2010, pp.1-4. [70] S.-J. Bae, Y.-S. Sohn, T.-Y. Oh, S.-H. Kim, Y.-S. Yang, D.-H. Kim, S.-H. Kwak, H.-S. Seol, C.-H. Shin, M.-S. Park, G.-H. Han, B.-C. Kim, Y.-K. Cho, H.-R. Kim, S.-Y. Doo, Y.-S. Kim, D.-S. Kang, Y.-R. Choi, S.-Y. Bang, S.-Y. Park, Y.-J. Shin, G.-S. Moon, C.-G. Park, W.-S. Kim, H.-J. Yang, J.-D. Lim, K.-I. Park, J. S. Choi, and Y.-H. Jun, “A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 498–499. [71] J. L. Zerbe, P. S. Chau, C. W. Werner, W. F. Stonecypher, H. J. Liaw, G. J. Yeh, T. P. Thrush, S. C. Best, K. S. Donnelly, “A 2Gb/s/pin 4-PAM parallel bus interface with transmit crosstalk cancellation, equalization, and integrating receivers,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2001, pp. 66–67. [72] K.-J. Sham, M. R. Ahmadi, S. B. G. Talbot, and R. Harjani, “FEXT crosstalk cancellation for high-speed serial link design,” in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2006, pp. 405–408. [73] J.-H. Bae, Y.-S. Sohn, S.-J. Bae, K.-I. Park, J.-S. Choi, Y.-H. Jun, J.-Y. Sim, and H.-J. Park, “A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel,” in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2010, pp. 1-4. [74] M. H. Nazari and A. Emami-Neyestanak, “A 15Gb/s 0.5mW/Gb/s 2-tap DFE receiver with far-end crosstalk cancellation,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 446–447. [75] T. Oh and R. Harjani, “A 6-Gb/s MIMO crosstalk cancellation scheme for high-speed I/Os,” IEEE J. Solid-State Circuits, vol. 46, no.8, pp.1843–1856, Aug. 2011. [76] J. Lee, W. Lee, and S. Cho, “A 2.5-Gb/s on-chip interconnect transceiver with crosstalk and ISI equalizer in 130nm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 1, pp. 124–136, Jan. 2012. [77] S.-K. Lee, H. Ha, H.-J. Park, and J.-Y. Sim, “A 5Gb/s single-ended parallel receiver with adaptive FEXT cancellation,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2012, pp. 140–141. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15904 | - |
| dc.description.abstract | 在串列連結應用中，當資料傳輸率達到每秒可傳送數億位元時，由於有限的頻寬使通道損耗變得嚴重。由通道的集膚效應和介電損失所引起的符際干擾會使收到資料的時間抖動變差，並惡化位元錯誤率。 為了增加資料頻寬，在多通道通訊系統中採用了平行介面傳輸，但產生的遠端干擾也會使時間抖動變差。此外，供應電壓雜訊會干擾對雜訊靈敏的類比電路並使其效能變差。
在本論文中，主要有五個部份。 在第二章中，在0.18微米CMOS製程下，實現一個1.5GHz的鎖相迴路，並具有壓抑供應電壓靈敏度的數位校正技巧。供應電壓雜訊模型的帶通特性亦被分析。在第三章中，在0.13微米CMOS製程下，實現一個1.62/2.7-Gb/s具有預先增強的可適性傳送機。其使用傳遞時間偵測器去量測傳遞時間並且調整閥係數。 在第四章中，在65奈米CMOS製程下，實現一個20-Gb/s 具有預先增強的可適性傳送機。其使用時間對數位轉化器去量測傳遞時間並且調整閥係數。在沒有使用回溯通道或共同合作的接收機情況下，此傳送機可達到低功率。在第五章中，在65奈米CMOS製程下，實現一個7.5-Gb/s具有可適性遠端干擾消除和前饋式等化器的傳送機。其使用責任週期偵測器去量測責任週期變化量並且調整干擾消除器的可適性係數。在第六章中，在40奈米CMOS製程下，實現一個10-Gb/s同時具有可適性干擾消除器和決策回授等化器的接收機。藉由使用雙迴路功率偵測技巧去數位校正兩者的閥係數。 | zh_TW |
| dc.description.abstract | As the data rate rises up to multi-gigabits per second in serial-link applications, the channel loss becomes severe due to the limited bandwidth. The inter-symbol interference (ISI) caused by skin effect and dielectric loss of the channel may degrade the timing jitter of received data and worsen the bit error rate (BER). To enhance the data bandwidth, the parallel interface is adopted in multi-channel communication. The far-end crosstalk (FEXT) may also degrade the timing jitter. Besides, the power supply noise may interfere with the noise-sensitive analog circuits to degrade the performance.
In this dissertation, there are mainly five parts. In chapter 2, a digitally-calibrated technique to suppress the supply voltage sensitivity of a 1.5GHz phase-locked loop (PLL) is realized in a 0.18-μm CMOS technology. The band-pass characteristic for the supply noise model is also analyzed. In chapter 3, a 1.62/2.7-Gb/s adaptive transmitter with pre-emphasis is realized in a 0.13-μm CMOS technology. The propagation-time detector is used to measure the propagation time and adjust the tap coefficients. In chapter 4, a 20-Gb/s adaptive transmitter with pre-emphasis is realized in a 65-nm CMOS process. The time-to-digital converter is used to measure the propagation time and adjust the tap coefficients. This transmitter has a low power without the back channels or the collaborating receiver. In chapter 5, a 7.5-Gb/s transmitter with adaptive FEXT cancellation and a feed-forward equalizer is realized in a 65-nm CMOS process. The duty cycle detector is used to measure the duty cycle variation and adjust the adaptation coefficient of a crosstalk canceller. In chapter 6, a 10-Gb/s receiver with simultaneously adaptive crosstalk canceller and decision-feedback equalizer is realized in a 40-nm CMOS technology. The tap coefficients of both are digitally calibrated by using the dual-loop power detection. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-07T17:54:58Z (GMT). No. of bitstreams: 1 ntu-101-F95943011-1.pdf: 13737536 bytes, checksum: 8ad3da3ee883417c216ab0406e1e5ebb (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | Contents
1. Introduction 1 1.1 Motivation 1 1.2 Organization 4 2. A Digitally-Calibrated Phase-Locked Loop with Supply Sensitivity Suppression 5 2.1 Introduction 6 2.2 Analysis and Suppression for Supply Voltage Sensitivity 7 2.3 Circuit Description 15 2.4 Experimental Results 20 2.5 Conclusion 30 3. A 1.62/2.7-Gb/s Adaptive Transmitter Using a Propagation-Time Detector 33 3.1 Introduction 34 3.2 Propagation-time Detection 35 3.3 Circuit Description 38 3.4 Experimental Results 43 3.5 Conclusion 49 4. A 20-Gb/s Transmitter with Adaptive Preemphasis in 65-nm CMOS Technology 51 4.1 Introduction 52 4.2 Time-to-digital Conversion 53 4.3 Circuit Description 56 4.4 Experimental Results 62 4.5 Conclusion 68 5. A 7.5-Gb/s One-Tap-FFE Transmitter with Adaptive FEXT Cancellation Using Duty Cycle Detection 69 5.1 Introduction 70 5.2 Adaptive Crosstalk Cancellation Algorithm 71 5.3 Circuit Description 82 5.4 Experimental Results 89 5.5 Conclusion 101 6. A 10-Gb/s Receiver with Simultaneously Adaptive XTC and DFE Using Power Detection 103 6.1 Introduction 104 6.2 Circuit Description 106 6.3 Experimental Results 117 6.4 Conclusions 125 7. Conclusion 127 7.1 Conclusion 127 7.2 Future Work 128 Bibliography 129 | |
| dc.language.iso | en | |
| dc.subject | 可適性傳送機 | zh_TW |
| dc.subject | 可適性接收機 | zh_TW |
| dc.subject | 多通道通訊 | zh_TW |
| dc.subject | 串接式通訊 | zh_TW |
| dc.subject | 鎖相迴路 | zh_TW |
| dc.subject | multi-channel application | en |
| dc.subject | adaptive receiver | en |
| dc.subject | adaptive transmitter | en |
| dc.subject | phase-locked loop | en |
| dc.subject | serial-link application | en |
| dc.title | 應用於多通道串接式通訊之鎖相迴路與可適性收發機 | zh_TW |
| dc.title | Phase-Locked Loop and Adaptive Transceiver for Multi-Channel Serial-Link Application | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-2 | |
| dc.description.degree | 博士 | |
| dc.contributor.oralexamcommittee | 郭泰豪,李泰成,鄭國興,洪誌銘,李朝政 | |
| dc.subject.keyword | 鎖相迴路,可適性傳送機,可適性接收機,多通道通訊,串接式通訊, | zh_TW |
| dc.subject.keyword | phase-locked loop,adaptive transmitter,adaptive receiver,multi-channel application,serial-link application, | en |
| dc.relation.page | 139 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2012-08-16 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-101-1.pdf 未授權公開取用 | 13.42 MB | Adobe PDF |
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