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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 黃俊郎 | |
dc.contributor.author | Shih-Hsuan Lin | en |
dc.contributor.author | 林士軒 | zh_TW |
dc.date.accessioned | 2021-06-07T17:54:09Z | - |
dc.date.copyright | 2012-08-20 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-08-17 | |
dc.identifier.citation | [1] M. Hashizume, T. Nishida, H. Yotsuyanagi, T. Tamesada, and Y. Miuram, “Testable Design of Resistor String DACs,” in Electronic Design, Test and Applications, 2006.
[2] M. Hashizume, Y. Hata, T. Nishida, H. Yotsuyanagi, and Y. MiuraCurrent, “Testable Design of Resistor String DACs,” in Asian Test Symposium, 2007, pp.399-403. [3] K. Arabi, K. Kaminska, and M. Sawan, “On chip testing data converters using static parameters,” IEEE Transactions on VLSI Systems, vol. 6, no. 3, pp. 409–419, 1998. [4] Y. Wen and K. Lee, “BIST structure for DAC testing,” IEEE Electronics Letters, vol. 34, no. 12, pp. 1173–1174, 1998. [5] J.-L. Huang, C.-K. Ong, and K.-T. Cheng, “A BIST scheme for on-chip ADC and DAC testing,” in Design, Automation & Test in Europe, 2000, pp. 216–220. [6] S. Chang, C. Lee, and J. Chen, “BIST scheme for DAC testing,” IEEE Electronics Letters, vol. 38, no. 15, pp. 776–777, 2002. [7] V. Kerzerho, P. Cauvet, S. Bernard, F. Azais, M. Comte, and M. Renovell, “A novel DFT technique for testing complete sets of ADCs and DACs in complex SiPs,” IEEE Design & Test of Computers, vol. 23, no. 3, pp. 234–243, 2006. [8] H. Xing, D. Chen, and R. Geiger, “On-chip at-speed linearity testing of high-resolution high-speed DACs using DDEM ADCs with dithering,” in Electro/Information Technology, 2008, pp. 117–122. [9] H. Son, J. Jang, Y. Kim, K. Kim, I. Kim, and S. Kang, “A BIST architecture for multiple DACs in an LTPS TFT-LCD source driver IC,” in International SoC Design Conference, 2009, pp. 120–123. [10] J.-J. Huang, C.-C. Li, and J.-L. Huang, “Testing LCD source driver IC with Built-on-Scribe-Line test circuitry,” in Asian Test Symposium, 2008, pp. 117–122. [11] W.-A. Lin, C.-C. Li, and J.-L. Huang, “Sigma-delta modulation based wafer-level testing for TFT-LCD source driver ICs,” in VLSI Test Symposium, 2011, pp. 315–320. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15871 | - |
dc.description.abstract | 測試平面顯示器源極驅動器晶片是在生產晶片中一個高成本的步驟。需要大量的類比量測和大量測試點是造成高成本最主要的原因。
在這篇論文中,我們提出一個方法去測試源極驅動器晶片,而這個方法可以讓我們在較短的時間內完成測試。我們對測試一個有著1,000通道和8位元精準度的數位類比轉換器的短路和斷路做為目標,運用在電源供應器觀察電流的方式去對它做測試。為了增加我們可以測到的範圍,我們加了兩種可測試性設計技術;參照多工器和回流多工器。參照多工器是用來增加在正常電路和異常電路的電流的差異,如此一來我們可以增進我們的測試精準度。而回流多工器是用來建造一個用來測試斷路的回流電流。此外,我們提出一個輪轉測試資料的方法來增加測試平行度。因為平行測試我們降低了更大量的類比量測次數。而我們最後會使用HSPICE的模擬來驗證這個方法的正確性跟有效性。 | zh_TW |
dc.description.abstract | Testing flat panel display source driver ICs is a costly process in manufacture; the root cause is the huge amount of analog measurements and analog access points required to test the internal DAC (digital-to-analog) array.
In this thesis, a scheme for testing source driver ICs is presented with a great gain in time efficiency. We test the open and short defects in a 1,000-channel 8-bit DAC by measuring the current from Gamma voltage source pins. To improve the fault coverage, two DfT techniques are proposed: REF-multiplexer (Reference multiplexer) and FB-multiplexer (Flow back multiplexer). REF-multiplexers enlarge the current deviation from faulty circuit to fault free one, thus we can improve the test accuracy. FB-multiplexer establishes the flow-back current to test open fault. Moreover, rotating pattern scheme is proposed to improve the test parallelism. By concurrent testing, we can test multiple channels in parallel and thus reduce great amount of analog measurement. The validity and the effectiveness of the proposed method are verified by HSPICE simulation. | en |
dc.description.provenance | Made available in DSpace on 2021-06-07T17:54:09Z (GMT). No. of bitstreams: 1 ntu-101-R99921082-1.pdf: 1249913 bytes, checksum: 76ca2e6143673330e048fb1bcdc33088 (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | 口試委員會審定書 i
誌謝 ii 中文摘要 iii Abstract iv Table of Contents v List of Figures vii List of Tables ix Chapter 1 Introduction 10 1.1. Motivation 10 1.2. Contributions 13 Chapter 2 Preliminaries 15 2.1. TFT-LCD Source Driver 15 2.2. DAC Structure 16 2.3. The DAC Array Fault Model 21 2.3.1. Open fault 21 2.3.2. Short fault 22 2.4. Related work 23 Chapter 3 Proposed Scheme 25 3.1. The DfT Architecture 25 3.1.1. Reference Voltage Multiplexer 26 3.1.2. Flow-Back Multiplexer 27 3.2. Short Fault Activation and Detection 28 3.2.1. Short Fault Effect Observation 28 3.2.2. Multi-channel Short Fault Detection 30 3.2.3. Why Reference Voltage Multiplexer 30 3.2.4. Decision of Reference Multiplexer Position 32 3.3. Open Fault Activation and Detection 35 3.3.1. Create a Flow-Back Current 35 3.3.2. Open Fault Effect Observation 37 3.3.3. Implementation of Flow-Back Multiplexer 39 3.3.4. Decision of Flow-Back Multiplexer Position 40 3.3.5. Rotating Pattern 45 Chapter 4 Simulation Results 48 4.1. Short Fault Simulation Results 48 4.1.1. Simulation result of 32-channel DAC with short fault in level 0 48 4.1.2. Result of 32-channel DAC with short fault in level 0 to level 7 51 4.2. Open Fault 54 4.2.1. Simulation result of 128-channel DAC 54 4.2.2. Simulation result of 32-channel DAC 57 4.2.3. Simulation result of single-channel DAC without DFT beside resistor string 60 4.2.4. Simulation result of 32-channel DAC without rotating pattern 62 4.3. Discussion 64 Chapter 5 Conclusion 67 | |
dc.language.iso | zh-TW | |
dc.title | 平面顯示器源極驅動器晶片可測試性設計技術 | zh_TW |
dc.title | A Design-for-Test Technique for Flat Panel Display Source Driver ICs | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 李建模,洪浩喬,陳竹一 | |
dc.subject.keyword | 平面,顯示器,源極驅動器,晶片,可測試性,設計技術, | zh_TW |
dc.subject.keyword | Design-for-Test,Technique,Flat Panel Display,Source Driver,ICs, | en |
dc.relation.page | 69 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2012-08-17 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
顯示於系所單位: | 電機工程學系 |
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